公开(公告)号：US20080038583A1

公开(公告)日：2008-02-14

申请号：US10584413

申请日：2003-12-25

申请人： Yuichiro Itai ,  Tasuku Satoh ,  Yoshiaki Sakamoto ,  Toshiro Takahashi ,  Masaru Kinoshita

发明人： Yuichiro Itai ,  Tasuku Satoh ,  Yoshiaki Sakamoto ,  Toshiro Takahashi ,  Masaru Kinoshita

IPC分类号： B32B9/00 ,  B05D5/12 ,  H01J19/40

CPC分类号： H01L51/0054 ,  H01L51/006 ,  H01L51/0071 ,  H01L51/0072 ,  H01L51/0081 ,  H01L51/5088 ,  H01L2251/5346

摘要： An object of the present invention is to enable suppression of a leak current of an organic EL element while improving a conductivity of the organic EL element and suppressing an operation voltage thereof. An organic EL element is used which comprises at least a luminescent layer, a hole transport layer adjacent to a positive-electrode side of the luminescent layer, and an electron injection transport layer adjacent to a negative-electrode side of the luminescent layer, wherein a hole injection layer is provided between the hole transport layer and the positive electrode, and the conductivity of the hole injection layer continuously changes along a thickness direction of the hole injection layer.

摘要翻译： 本发明的目的在于提供有机EL元件的导电性并抑制其工作电压，能够抑制有机EL元件的漏电流。 使用有机EL元件，其至少包括发光层，与发光层的正极侧相邻的空穴传输层和与发光层的负极侧相邻的电子注入传输层，其中， 空穴注入层设置在空穴传输层和正极之间，空穴注入层的导电性沿空穴注入层的厚度方向连续变化。

公开(公告)号：US20060279202A1

公开(公告)日：2006-12-14

申请号：US11441204

申请日：2006-05-26

申请人： Yoshiaki Sakamoto ,  Toshiro Takahashi

发明人： Yoshiaki Sakamoto ,  Toshiro Takahashi

IPC分类号： H05B33/00 ,  H01L51/50 ,  B05D5/06 ,  B05D5/12 ,  B05C11/11

CPC分类号： H01L51/5212 ,  H01L27/3244 ,  H01L51/0021 ,  H01L2251/5315

摘要： In an organic electroluminescent display device comprising a wiring layer, an insulating layer, a first electrode, an organic electroluminescent layer, and a second electrode, wiring which conducts with a second electrode is arranged between light emitting pixels, and is provided either between an organic electroluminescent layer and the second electrodes, or on top of the second electrodes.

摘要翻译： 在包括布线层，绝缘层，第一电极，有机电致发光层和第二电极的有机电致发光显示装置中，与第二电极导通的布线布置在发光像素之间，并且设置在有机 电致发光层和第二电极，或在第二电极的顶部。

公开(公告)号：US06946876B2

公开(公告)日：2005-09-20

申请号：US10705858

申请日：2003-11-13

申请人： Takeshi Isezaki ,  Toshiro Takahashi

发明人： Takeshi Isezaki ,  Toshiro Takahashi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/10 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/175

CPC分类号： H03K19/00361

摘要： Noise of a low frequency band, generated inside a logic circuit, is remarkably reduced. A semiconductor integrated circuit device is provided with: a high voltage supply circuit generating, from a high voltage external power supply that is externally input, a high voltage internal power supply having a certain voltage level; and a low voltage supply circuit generating, from a low voltage external power supply that is externally input, a low voltage internal power supply having a certain voltage level. In inputting/outputting a signal between a logic circuit block and an I/O unit, a signal level is shifted through a level shifter unit. Since the logic circuit block is operated by the high voltage internal power supply and the low voltage internal power supply, the inductance in the semiconductor integrated circuit device is not subjected directly to DC fluctuation in consumed currents. Therefore, the characteristic impedance of power supply becomes equivalently smaller, thereby reducing low frequency noise.

摘要翻译： 在逻辑电路内产生的低频带的噪声显着降低。 半导体集成电路器件具有：从外部输入的高压外部电源产生具有一定电压电平的高压内部电源的高压电源电路; 以及从外部输入的低压外部电源产生具有一定电压电平的低压内部电源的低电压电源电路。 在逻辑电路块和I / O单元之间输入/输出信号时，信号电平通过电平移位器单元移位。 由于逻辑电路块由高压内部电源和低电压内部电源操作，因此半导体集成电路器件中的电感不会直接受到消耗电流中的直流波动的影响。 因此，电源的特性阻抗变得相当小，从而降低了低频噪声。

公开(公告)号：US06774695B2

公开(公告)日：2004-08-10

申请号：US09976052

申请日：2001-10-15

申请人： Hirokatsu Hayashi ,  Toshiro Takahashi

发明人： Hirokatsu Hayashi ,  Toshiro Takahashi

IPC分类号： H03K19185

CPC分类号： H03K19/00323

摘要： A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.

摘要翻译： 电平转换电路由电平移位电路构成，电平移位电路用于提供与输入信号相同相位的电平转换信号和与其相反的信号，以及响应于较早的输出信号的后续电路 电平移位电路，用于产生输出信号，其中后续电路由反相电路组成，其中两个p沟道型MOS晶体管和两个n沟道型MOS晶体管串联连接在第一电压端和第二电压之间 端子，其中一对用作输入晶体管，并且剩余的一对晶体管基于电平移位电路的输出信号进行反馈，以快速响应下一个变化。

公开(公告)号：US06468600B1

公开(公告)日：2002-10-22

申请号：US10067013

申请日：2002-02-04

申请人： Susumu Yoshida ,  Yuichiro Itai ,  Yoshiharu Kasamatsu ,  Toshiro Takahashi

发明人： Susumu Yoshida ,  Yuichiro Itai ,  Yoshiharu Kasamatsu ,  Toshiro Takahashi

IPC分类号： B05D306

CPC分类号： G11B5/8404

摘要： A method of texturing includes the process of enhancing the hydrophilicity on the surface of a substrate for a recording medium. A texture is then formed on the surface of the substrate with an aqueous slurry in which abrasive grains are dispersed. The surface of the substrate is expected to exhibit an enhanced property of wetness to the aqueous slurry. The aqueous slurry easily spreads over and contacts the surface of the substrate even from the initial stage of the process. The abrasive grains in the aqueous slurry are allowed to uniformly spread over the surface of the substrate. Establishment of the texture can be started on the surface of the substrate at an earlier stage of the process. Even with the abrasive grains of a smaller grain size, a fine and uniform texture of a predetermined surface roughness can be established on the surface of the substrate within a shortened period. Increase in the operating period of abrasion can remarkably be suppressed irrespective of the reduced size of the abrasive grains.

摘要翻译： 纹理化方法包括提高用于记录介质的基材表面上的亲水性的方法。 然后在其中分散磨料颗粒的水性浆料在基材的表面上形成织构。 预期基材的表面具有增强的水性浆液的润湿性能。 即使从工艺的初始阶段，含水浆料也容易扩散并接触基材的表面。 允许含水浆料中的磨料颗粒均匀地铺展在基材的表面上。 可以在该方法的较早阶段在衬底的表面上开始纹理的建立。 即使具有较小晶粒尺寸的磨粒，可以在缩短的时间内在衬底的表面上形成预定表面粗糙度的精细且均匀的织构。 无论磨粒的尺寸减小，磨损操作周期的增加都可以被显着抑制。

公开(公告)号：US06433398B1

公开(公告)日：2002-08-13

申请号：US09661372

申请日：2000-09-13

申请人： Kazuhisa Suzuki ,  Toshiro Takahashi ,  Yasunobu Yanagisawa ,  Yusuke Nonaka

发明人： Kazuhisa Suzuki ,  Toshiro Takahashi ,  Yasunobu Yanagisawa ,  Yusuke Nonaka

IPC分类号： H01L2972

CPC分类号： H01L27/0629 ,  Y10S438/981

摘要： A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

摘要翻译： 通过利用比构成CMOS栅极阵列的逻辑部分的MISFET更厚的栅极氧化膜9B形成具有小的漏电流的电容元件C1，而不增加制造CMOS门阵列的步骤数。 电容元件C1是栅电极10E。 栅电极10E的一部分由多晶硅膜制成。 多晶硅膜掺杂有n型杂质，使得即使在低电源电压下，电容元件也可以可靠地工作。

公开(公告)号：US6087879A

公开(公告)日：2000-07-11

申请号：US736694

申请日：1996-10-25

申请人： Toshiro Takahashi ,  Kazuo Koide

发明人： Toshiro Takahashi ,  Kazuo Koide

IPC分类号： G01R31/28 ,  H03K3/356 ,  H03K19/0175 ,  H03K19/0948 ,  H03K5/01

CPC分类号： H03K3/356121

摘要： When signal transmission is performed between two semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an operating voltage of the two semiconductor integrated circuit devices, a received signal is held in the receiving semiconductor integrated circuit device in synchronization with the clock signal while the small signal amplitude of the held signal is kept substantially without change. The received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit to a subsequent latch circuit of the receiving semiconductor integrated circuit device.

摘要翻译： 当使用相对于两个半导体集成电路器件的工作电压的小的信号幅度与时钟信号同步地在两个半导体集成电路器件之间执行信号传输时，接收信号与接收半导体集成电路器件同步地保持在接收半导体集成电路器件中 同时保持信号的小信号幅度基本上保持不变。 具有小信号幅度的接收信号沿着包括组合逻辑电路的信号传输路径被放大到接收半导体集成电路器件的后续锁存电路。

公开(公告)号：US5941673A

公开(公告)日：1999-08-24

申请号：US27181

申请日：1998-02-20

申请人： Minoru Hayakawa ,  Toshiro Takahashi

发明人： Minoru Hayakawa ,  Toshiro Takahashi

IPC分类号： B21D28/36 ,  B21D43/00 ,  B21D43/04 ,  B21D43/20 ,  B21D43/24 ,  B23Q7/10 ,  B65D19/38 ,  B65H1/00 ,  B65B21/02

CPC分类号： B21D43/20 ,  B23Q7/103

摘要： A sheet material loading and unloading apparatus comprises: a frame having a lower frame and an upper frame attached to the lower frame in such a manner as to freely move to a vertical direction; a vertically movable lifter disposed within the frame; a truck going in and out over the lifter; a plurality of pallets supporting a material or a processed product; a plurality of escapable loading positioning members being disposed in the upper frame; a plurality of escapable material supporting members being disposed in the upper frame; and a carriage being disposed within the frame.

摘要翻译： 片材装卸装置包括：框架，具有下框架和上框架，以便自由移动到垂直方向的方式附接到下框架; 设置在框架内的可升降升降器; 一辆卡车进出升降机; 支撑材料或加工产品的多个托盘; 多个可脱开的装载定位构件设置在上框架中; 多个可逸出材料支撑构件设置在上框架中; 以及设置在框架内的托架。

公开(公告)号：US5872471A

公开(公告)日：1999-02-16

申请号：US773307

申请日：1996-12-24

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Akira Yamagiwa ,  Toshitsugu Takekuma ,  Toshiro Takahashi ,  Tatsuhiro Aida

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Akira Yamagiwa ,  Toshitsugu Takekuma ,  Toshiro Takahashi ,  Tatsuhiro Aida

IPC分类号： H03K19/0185 ,  H04L5/14 ,  H03K17/00

CPC分类号： H03K19/018592 ,  H04L5/1423

摘要： In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.

摘要翻译： 在用于经由传输线在LSI之间进行同时双向通信的同时双向传输电路中，连接到传输线的输入/输出电路被包括在LSI中。 输入/输出电路具有驱动器和接收器。 驱动器根据LSI内的逻辑信号将输出信号发送到传输线。 接收机通过传输线接收具有接收信号和输出信号的混合的混合信号。 由LSI中的接收机接收到的信号已被另一方发送到传输线，即与其通信的另一个LSI。 接收器也接收逻辑信号输出。 接收导出混合信号和逻辑信号输出之间的差异，从而从混合信号中去除逻辑信号的分量，并输出接收信号。 接收器具有用于接收逻辑信号并将其输出到偏置电路的参考电路，用于产生与参考电路的内部电阻相分离的电压信号的偏置电路，以及用于接收混合信号和分频的差分接收器 电压信号并输出​​它们之间的差异。 参考电路和偏置电路通过使用MOS晶体管形成。

公开(公告)号：US5809039A

公开(公告)日：1998-09-15

申请号：US603502

申请日：1996-02-20

申请人： Toshiro Takahashi ,  Fumihiko Shirotori ,  Kaoru Moriwaki ,  Masahiko Nagai

发明人： Toshiro Takahashi ,  Fumihiko Shirotori ,  Kaoru Moriwaki ,  Masahiko Nagai

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/00 ,  G11C29/00

CPC分类号： G01R31/318505

摘要： A logic LSI is divided into a plurality of functional blocks, and an output portion of each functional block is provided with a buffer circuit with a scan function which can change a function of latching data by a control signal and a function of making an input signal pass intact. The buffer circuit is connected to a test exclusive bus and the test data can be entered directly to the buffer or read out of the buffer. Test patterns are generated in each functional block and diagnosis can be carried out in each functional block. When the functional block is used in other LSI, since the test patterns already generated can be utilized, the time required for generation of test patterns and for the test can be significantly reduced.

摘要翻译： 逻辑LSI被分成多个功能块，并且每个功能块的输出部分设置有具有扫描功能的缓冲电路，该扫描功能可以通过控制信号改变锁存数据的功能，并且具有使输入信号 传球完好无损。 缓冲电路连接到测试专用总线，测试数据可以直接输入缓冲区或读出缓冲区。 在每个功能块中产生测试模式，并且可以在每个功能块中进行诊断。 当在其他LSI中使用功能块时，由于可以利用已经产生的测试图案，所以可以显着地减少产生测试图案和测试所需的时间。