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97 条记录 (耗时 0.031 秒)

    Method of reducing wordline shorting
    72.
    发明授权
    Method of reducing wordline shorting 有权
    减少字线短路的方法

    公开(公告)号：US08445346B2

    公开(公告)日：2013-05-21

    申请号：US12611614

    申请日：2009-11-03

    申请人： Hong-Ji Lee ,  Nan-Tsu Lian ,  Kuang-Chao Chen

    发明人： Hong-Ji Lee ,  Nan-Tsu Lian ,  Kuang-Chao Chen

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/28247 ,  H01L21/28282 ,  H01L27/11568

    摘要： A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.

    摘要翻译： 一种制造存储器件的方法包括提供具有绝缘层的衬底，在绝缘层上形成第一，第二和第三导电层，在第三导电层上形成掩模，蚀刻通过第三导电层和第一部分厚度 使用所述掩模提供所述第三导电层的蚀刻侧壁部分和所述第二多晶硅层的蚀刻的上表面，以及沿着蚀刻的侧壁部分和所蚀刻的上表面形成衬垫层。

    Method of manufacturing flash memory
    75.
    发明授权
    Method of manufacturing flash memory 有权
    闪存制造方法

    公开(公告)号：US06887757B2

    公开(公告)日：2005-05-03

    申请号：US10249867

    申请日：2003-05-14

    申请人： Kuang-Chao Chen ,  Hsueh-Hao Shih ,  Ling-Wuu Yang

    发明人： Kuang-Chao Chen ,  Hsueh-Hao Shih ,  Ling-Wuu Yang

    IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/105

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate. The second conductive layer over the peripheral circuit region is similarly patterned to form a gate.

    摘要翻译： 提供一种制造闪速存储器件的方法。 首先，提供分割为存储单元区域和外围电路区域的基板。 在存储单元区域上形成隧道介电层，并在外围电路区域上形成衬垫层。 此后，在衬底上形成图案化的栅极导电层。 栅极间电介质层和钝化层依次形成在衬底上。 外围电路区域上的钝化层，栅极间电介质层，栅极导电层和衬垫层被去除。 在外围电路区域上形成栅极电介质层，同时将存储单元区域上的钝化层转换成氧化物层。 在衬底上形成另一导电层。 将存储单元区域上的导电层，氧化物层，栅极间电介质层和栅极导电层图案化以形成存储栅极。 外围电路区域上的第二导电层类似地构图形成栅极。

    Method of forming a capacitor of a dram cell
    76.
    发明授权
    Method of forming a capacitor of a dram cell 失效
    形成电容器电容器的方法

    公开(公告)号：US5811344A

    公开(公告)日：1998-09-22

    申请号：US789495

    申请日：1997-01-27

    申请人： Tuby Tu ,  Kuang-Chao Chen ,  May Wang

    发明人： Tuby Tu ,  Kuang-Chao Chen ,  May Wang

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/72

    CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86

    摘要： The present invention relates to a stacked capacitor of a DRAM cell, particully remarkably increasing a surface area of a storage electrode of a stacked capacitor without increasing an occupation area and a complexity of fabrication thereof. According to the invention, by use of depositing a protection polysilicon layer on a rugged polysilicon layer, which can provide an increased surface area of a storage electrode, a chemical oxide layer underlying the rugged polysilicon layer is protected by the protection polysilicon layer during a HF dip and thus a peeling of the rugged polysilicon layer as a result of the chemical oxide loss will not occur, thereby preventing a production yield loss.

    摘要翻译： 本发明涉及一种DRAM单元的叠层电容器，其特征在于显着地增加了层叠电容器的存储电极的表面积，而不增加占用面积及其制造的复杂性。 根据本发明，通过在保持多晶硅层上沉积保护多晶硅层，其可以提供存储电极的增加的表面积，在耐久性多晶硅层下面的化学氧化物层在HF期间被保护多晶硅层保护 因此不会发生由于化学氧化物损失导致的粗糙多晶硅层的剥离，从而防止了生产成品率的损失。

    Aluminum plug process
    77.
    发明授权
    Aluminum plug process 失效
    铝塞过程

    公开(公告)号：US5356836A

    公开(公告)日：1994-10-18

    申请号：US108224

    申请日：1993-08-19

    申请人： Kuang-Chao Chen ,  Shaw-Tzeng Hsia

    发明人： Kuang-Chao Chen ,  Shaw-Tzeng Hsia

    IPC分类号： C23C14/34 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L21/283

    CPC分类号： H01L21/76858 ,  H01L21/743 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

    摘要： A new method of metallization of an integrated circuit is described. This method can be used for a first metallization to contact the semiconductor substrate regions or for a subsequent metallizations for interconnection within the integrated circuit. An insulating layer is provided over the surface of a semiconductor substrate or over a metallization layer. At least one contact opening is made through the insulating layer to the semiconductor substrate or to the metallization layer. A barrier metal layer is deposited over the surface of the substrate and within the contact opening wherein most of the barrier metal is deposited on the bottom of the contact opening rather than on the sides of the opening. A metal layer is cold sputtered over the barrier metal layer, then the metal is hot sputtered over the cold-sputtered metal layer wherein the cold and hot sputtering are continuous operations to complete the metallization of the integrated circuit.

    摘要翻译： 描述了集成电路的金属化的新方法。 该方法可以用于第一金属化以接触半导体衬底区域或用于随后的集成电路内的互连金属化。 绝缘层设置在半导体衬底的表面上或金属化层上。 至少一个接触开口穿过绝缘层到达半导体衬底或金属化层。 阻挡金属层沉积在衬底的表面上并且在接触开口内，其中大部分阻挡金属沉积在接触开口的底部而不是在开口的侧面上。 金属层在阻挡金属层上被冷溅射，然后将金属热溅射在冷溅射的金属层上，其中冷和热溅射是连续操作以完成集成电路的金属化。

    EXTERNAL ELECTRONIC EAR DEVICE AND COCHLEAR IMPLANT DEVICE
    78.
    发明申请
    EXTERNAL ELECTRONIC EAR DEVICE AND COCHLEAR IMPLANT DEVICE 有权
    外部电子耳设备和COCHLEAR IMPLANT DEVICE

    公开(公告)号：US20160206878A1

    公开(公告)日：2016-07-21

    申请号：US14996239

    申请日：2016-01-15

    申请人： Kuang-Chao Chen ,  SILICON MOTION, INC.

    发明人： Kuang-Chao Chen ,  Kuo-Liang Yeh

    IPC分类号： A61N1/36 ,  A61N1/372 ,  A61N1/375 ,  A61N1/05

    CPC分类号： A61N1/36032 ,  A61N1/0541 ,  A61N1/36036 ,  A61N1/37229 ,  A61N1/375

    摘要： An external electronic ear device includes a housing, an external magnet, a microphone, a processing circuit and a wireless signal transmitter circuit. The external magnet is disposed in the housing and attracts a receiver magnet disposed under a scalp of a user. The microphone is disposed in the housing and receives an external sound and generates a sound signal corresponding to the external sound. The processing circuit is disposed in the housing and converts the sound signal into an electrode driving signal. The wireless signal transmitter circuit is disposed in the housing and transmits the electrode driving signal to a cochlear implant device in the cochlear system. The cochlear implant device converts the electrode driving signal into a plurality of electrode currents, and a plurality of electrical pulses are generated in a cochlear nerve of the user through a plurality of electrodes according to the electrode currents.

    摘要翻译： 外部电子耳机包括壳体，外部磁体，麦克风，处理电路和无线信号发射器电路。 外部磁体设置在壳体中并吸引设置在使用者头皮下方的接收器磁体。 麦克风设置在外壳中并接收外部声音，并产生对应于外部声音的声音信号。 处理电路设置在壳体中并将声音信号转换成电极驱动信号。 无线信号发射器电路设置在外壳中，并将电极驱动信号传输到耳蜗系统中的人工耳蜗植入装置。 耳蜗植入装置将电极驱动信号转换为多个电极电流，并且根据电极电流通过多个电极在用户的耳蜗神经中产生多个电脉冲。

    Fabrication method for shallow trench isolation region
    80.
    发明授权
    Fabrication method for shallow trench isolation region 有权
    浅沟槽隔离区的制作方法

    公开(公告)号：US06911374B2

    公开(公告)日：2005-06-28

    申请号：US10604615

    申请日：2003-08-05

    申请人： Chin Hsiang Lin ,  Chin-Wei Liao ,  Hsueh-Hao Shih ,  Kuang-Chao Chen

    发明人： Chin Hsiang Lin ,  Chin-Wei Liao ,  Hsueh-Hao Shih ,  Kuang-Chao Chen

    IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/76232 ,  H01L21/31111 ,  H01L21/31155

    摘要： A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.

    摘要翻译： 描述了浅沟槽隔离区域的制造方法。 沟槽的一部分填充有第一绝缘层，随后进行表面处理工艺以在第一绝缘层的一部分的表面上形成表面处理层。 然后去除表面处理层，随后在第一绝缘层上形成第二绝缘层，并填充沟槽以形成浅沟槽隔离区域。 由于沟槽的一部分首先填充有第一绝缘层，接着除去第一绝缘层的一部分，沟槽的纵横比在填充沟槽中的第二绝缘体之前较低。 因此防止由于高纵横比而导致浅沟槽隔离区域中的空隙形成的不良结果。