公开(公告)号：US5754149A

公开(公告)日：1998-05-19

申请号：US543739

申请日：1995-10-16

申请人： Jim J. Browning ,  John K. Lee ,  Tyler A. Lowrey

发明人： Jim J. Browning ,  John K. Lee ,  Tyler A. Lowrey

IPC分类号： G09G3/00 ,  G09G3/20 ,  G09G3/22 ,  H01J31/12 ,  H04N5/70 ,  H04N17/04 ,  G09G3/10

CPC分类号： G09G3/006 ,  G09G3/22 ,  H01J31/127 ,  H04N5/70 ,  G09G2300/0809 ,  G09G3/2014 ,  H04N17/04

摘要： The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grids is coupled to a bus having a predetermined voltage by a link. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each of bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.

公开(公告)号：US5541872A

公开(公告)日：1996-07-30

申请号：US450916

申请日：1995-05-26

申请人： Tyler A. Lowrey ,  Wayne I. Kinney

发明人： Tyler A. Lowrey ,  Wayne I. Kinney

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.

摘要翻译： 这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在 主存电路。 第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。 第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化 铁电存储电路。 因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。 这又导致位线参考电压+ E，ovs BL + EE跟踪主存储器电路中的铁电电容器的电压变化，从而为BL和+ E，ovs BL + EE互补信号提供改善的余量 其由用于主存储器电路的多个读出放大器感测。

公开(公告)号：US5424975A

公开(公告)日：1995-06-13

申请号：US175923

申请日：1993-12-30

申请人： Tyler A. Lowrey ,  Wayne I. Kinney

发明人： Tyler A. Lowrey ,  Wayne I. Kinney

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.

摘要翻译： 这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在 主存电路。 第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。 第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化 铁电存储电路。 因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。 这又导致位线参考电压＆upbar＆B跟踪主存储器电路中的铁电电容器的电压变化，从而为由多个读出放大器感测的BL和＆amp; B和B互补信号提供改进的余量， 主存储电路。

公开(公告)号：US5372973A

公开(公告)日：1994-12-13

申请号：US53794

申请日：1993-04-27

申请人： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

发明人： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

IPC分类号： H01J1/304 ,  H01J9/02 ,  H01L21/3105 ,  H01L21/465

CPC分类号： H01J9/025 ,  H01L21/31053 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226

摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

摘要翻译： 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积 具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii） 化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料 。

公开(公告)号：US5283204A

公开(公告)日：1994-02-01

申请号：US869571

申请日：1992-04-15

申请人： Howard E. Rhodes ,  Tyler A. Lowrey

发明人： Howard E. Rhodes ,  Tyler A. Lowrey

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/76

CPC分类号： H01L27/10852 ,  H01L28/86

摘要： The invention is directed to maximizing storage cell surface area in a high density/high volume DRAM (dynamic random access memory) fabrication process. Fabrication methods are disclosed that, when used with existing capacitor fabrication processes, will reduce cell leakage and allow for increased capacitance. The present invention corrects any severed storage node poly that may have resulted from a misalignment of a masking pattern used for defining future buried contacts by placing passivation oxidation over the existing wafer surface which, in effect, seals off the severed storage node poly form the capacitor's top cell plate poly. The passivation oxidation prevents cell plate to plate leakage while protecting the severed storage node poly from subsequent deposition of conductive layers.

摘要翻译： 本发明旨在在高密度/高体积DRAM（动态随机存取存储器）制造过程中最大化存储单元表面积。 公开了制造方法，当与现有电容器制造工艺一起使用时，将减少电池泄漏并允许增加电容。 本发明通过在现有的晶片表面上放置钝化氧化来校正可能由用于定义未来埋入触点的掩模图案的未对准而导致的任何切断的存储节点poly，其实际上将切断的存储节点poly密封成电容器的 顶部细胞板聚 钝化氧化防止细胞板平板泄漏，同时保护切断的存储节点poly免于继续沉积导电层。

公开(公告)号：US5244842A

公开(公告)日：1993-09-14

申请号：US812061

申请日：1991-12-17

申请人： David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

发明人： David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

IPC分类号： H01L21/02 ,  H01L21/334

CPC分类号： H01L28/84 ,  H01L29/66181 ,  Y10S438/964

摘要： A method of increasing capacitance by surface roughening in semiconductor wafer processing includes the following steps: a) applying a first layer of material atop a substrate thereby defining an exposed surface; b) incontinuously adhering discrete solid particles to the first layer exposed surface to roughen the exposed surface; and c) applying a second layer of material atop the first layer and adhered solid particles to define an outer surface, the particles adhered to the first layer inducing roughness into the outer surface thereby increasing its surface area and accordingly capacitance of the second layer in the final wafer structure.

摘要翻译： 通过在半导体晶片处理中通过表面粗糙度增加电容的方法包括以下步骤：a）在基板顶部施加第一层材料，从而限定暴露的表面; b）不连续地将离散的固体颗粒粘附到第一层暴露表面以使暴露的表面粗糙; 以及c）在第一层上方施加第二层材料并粘附固体颗粒以限定外表面，粘附到第一层的颗粒引起粗糙度进入外表面，从而增加其表面积，从而增加其中的第二层的电容 最终的晶圆结构。

公开(公告)号：US5229331A

公开(公告)日：1993-07-20

申请号：US837453

申请日：1992-02-14

申请人： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

发明人： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

IPC分类号： H01J1/304 ,  H01J9/02 ,  H01L21/3105

CPC分类号： H01J9/025 ,  H01L21/31053 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226

摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

摘要翻译： 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积 具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii） 化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料 。

公开(公告)号：US5210472A

公开(公告)日：1993-05-11

申请号：US864702

申请日：1992-04-07

申请人： Stephen L. Casper ,  Tyler A. Lowrey

发明人： Stephen L. Casper ,  Tyler A. Lowrey

IPC分类号： G09G3/00 ,  G09G3/20 ,  G09G3/22 ,  H01J31/12

CPC分类号： G09G3/006 ,  G09G3/22 ,  H01J31/127 ,  G09G2300/0809 ,  G09G3/2014

摘要： A flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage. Although the invention was created with field-emission displays in mind, the technique may be used in any matrix-addressable display (e.g. vacuum fluorescent, electro-luminescent, or plasma-type displays) where high pixel activation voltages must be switched. In a preferred embodiment field emission display, emitter-to-grid voltage differential is maintained near zero during non-emission periods, and is raised to a level sufficient to cause emission by grounding pixel emitters at each row and column intersection through a pair of series-connected field-effect transistors (FETs). The emitter base electrode of each emitter node is coupled to the grid via a current-limiting transistor. Display brightness control is accomplished by varying the gate voltages of either FET, such that emission current can be adjusted. In addition, a fusible link is placed in series with the grounding path through the series-connected FETs. Gray scale shading is accompanied by varying the duty cycle of pixel actuation time as a percentage of frame time.

摘要翻译： 一种平板显示器，其中低电压行和列地址信号控制高得多的像素激活电压。 虽然本发明是考虑到场发射显示器而产生的，但是该技术可以用于必须切换高像素激活电压的任何矩阵可寻址显示器（例如，真空荧光灯，电致发光或等离子体型显示器）中。 在优选实施例的场致发射显示中，发射极间电压差在非发射期间保持接近于零，并且通过将每一行和列交叉点上的像素发射器通过一对串联而被提高到足以引起发射的水平 连接的场效应晶体管（FET）。 每个发射极节点的发射极基极通过限流晶体管耦合到电网。 通过改变两个FET的栅极电压来实现显示亮度控制，使得可以调节发射电流。 另外，通过串联连接的FET与接地路径串联放置熔丝。 灰度阴影伴随着像素致动时间的占空比以帧时间的百分比来改变。

公开(公告)号：US5134085A

公开(公告)日：1992-07-28

申请号：US796099

申请日：1991-11-21

申请人： Brent D. Gilgen ,  Tyler A. Lowrey ,  Joseph J. Karniewicz ,  Anthony M. McQueen

发明人： Brent D. Gilgen ,  Tyler A. Lowrey ,  Joseph J. Karniewicz ,  Anthony M. McQueen

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852

摘要： This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond. The process flow is characterized: reduced mask count due to the elimination of the N+ and p+ source-drain masking layers via the split polysilicon technique; an option to further reduce wafer processing by allowing the LOCOS stress relief (pad) oxide layer to later function as the transistor gate dielectric layer; N-channel device optimization via self-aligned punch-through and lightly-doped-drain (LDD) implants, without the addition of extra P-channel masking steps via the split poly approach; use of semi, self-aligned contact of bottom cell plate to access gate diffusion allowing tight spacing between bottom cell plate buried contact and access gate polysilicon; improved refresh characteristics achieved by avoiding reduction of isolation thickness due to the spacer oxide etch; improved refresh characteristics achieved by protecting the sensitive areas of the storage node from damage typically caused by a spacer oxide etch; improved refresh characteristics achieved by eliminating the high-dose N-channel source/drain implantation from the storage node side of the access transistor gate; and improved immunity to soft error upset achieved through the use of an optional self-aligned "Hi-C" implant that is performed without the addition of an extra masking step.

摘要翻译： 本发明构成了用于制造用于1兆比特或更大的叠层电容器类型的动态随机存取存储器的10-12掩模，分裂多晶硅工艺。 工艺流程的特征在于：通过分离多晶硅技术消除N +和p +源极 - 漏极掩蔽层，减少掩模计数; 通过允许LOCOS应力消除（焊盘）氧化物层稍后用作晶体管栅极介电层来进一步减少晶片加工的选择; 通过自对准穿通和轻掺杂漏极（LDD）种植体进行N沟道器件优化，而不需要通过分裂聚合法添加额外的P沟道掩蔽步骤; 使用底部单元板的半自动对准接触来访问栅极扩散，允许底部单元板掩埋触点和存取栅极多晶硅之间的紧密间隔; 通过避免由于间隔氧化物蚀刻而导致的隔离厚度的降低而获得的改进的刷新特性; 通过保护存储节点的敏感区域免受通常由间隔物氧化物蚀刻引起的损坏而实现的改善的刷新特性; 通过从存取晶体管栅极的存储节点侧消除高剂量N沟道源极/漏极注入而获得的改善的刷新特性; 并且通过使用在不添加额外掩蔽步骤的情况下执行的可选择的自对准“Hi-C”植入物来实现对软错误不舒服的改善的免疫力。

公开(公告)号：US5126290A

公开(公告)日：1992-06-30

申请号：US760026

申请日：1991-09-11

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/8246 ,  H01L23/525

CPC分类号： H01L27/11206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/90

摘要： The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory. With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

摘要翻译： 本发明提供了一种用于可编程只读存储器（PROM）的可编程结构，该可编程只读存储器利用在数字线上构造的单面臭氧间隔作为一次可编程节点。 氧化物/氮化物/氧化物层（ONO）用作下列平行的数字行行之间的接口，具有单面臭氧间隔物，并且在可编程只读存储器中覆盖字线的平行列。 通过在行/列矩阵中的每个字线下方通过的每个数字线形成，从而提供可编程数字/字线矩阵。 矩阵中的数字和字线的每个交叉点将通过在相关联的数字/字线导体之间施加适当的电压电位来破坏薄ONO电介质接口而被永久编程为一个或零。