METHOD OF FORMING SHALLOW TRENCH ISOLATIONS
    71.
    发明申请
    METHOD OF FORMING SHALLOW TRENCH ISOLATIONS 有权
    形成浅层分离的方法

    公开(公告)号:US20140322891A1

    公开(公告)日:2014-10-30

    申请号:US14329982

    申请日:2014-07-13

    Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.

    Abstract translation: 一种形成浅沟槽隔离结构的方法,包括以下步骤:在衬底中形成沟槽,填充沟槽下部的第一绝缘层并在沟槽的上部限定凹陷,在侧壁上形成缓冲层 在凹部中填充第二绝缘层,并执行蒸汽退火处理,以将围绕第一绝缘层的基板转变为氧化物层。

    PLUG STRUCTURE AND PROCESS THEREOF
    72.
    发明申请
    PLUG STRUCTURE AND PROCESS THEREOF 有权
    PLUG结构及其过程

    公开(公告)号:US20140264481A1

    公开(公告)日:2014-09-18

    申请号:US13802917

    申请日:2013-03-14

    Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

    Abstract translation: 提供包括第一电介质层,第二电介质层,阻挡层和第二插塞的插塞结构。 其中具有第一插头的第一电介质层位于衬底上,其中第一插头物理地接触衬底中的源极/漏极。 具有暴露第一插头的开口的第二电介质层位于第一电介质层上。 阻挡层保形地覆盖开口,其中阻挡层具有底部和侧壁部分,并且底部部分是单层,并且在侧壁部分是双层的同时物理地接触第一插塞。 第二个塞子填充开口和阻挡层。 此外,还提供了形成插头结构的工艺。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    73.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号:US20140264480A1

    公开(公告)日:2014-09-18

    申请号:US13802878

    申请日:2013-03-14

    Abstract: A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of the first dielectric layer. Then, a patterned mask is formed on the metal gate structure, and the patterned mask does not overlap the first dielectric layer. Subsequently, a second dielectric layer covering the patterned mask is conformally formed on the semiconductor substrate. Furthermore, a part of the first dielectric layer and a part of the second dielectric layer are removed for forming at least a contact hole.

    Abstract translation: 形成半导体器件的方法包括以下步骤。 首先,提供半导体衬底,并且在半导体衬底上设置金属栅极结构和第一电介质层,其中金属栅极结构的顶表面与第一电介质层的顶表面对齐。 然后,在金属栅极结构上形成图案化掩模,并且图案化掩模不与第一介电层重叠。 随后,覆盖图案化掩模的第二电介质层共形地形成在半导体衬底上。 此外,除去第一电介质层的一部分和第二电介质层的一部分以至少形成接触孔。

    Plug structure
    74.
    发明授权
    Plug structure 有权
    插头结构

    公开(公告)号:US08836129B1

    公开(公告)日:2014-09-16

    申请号:US13802917

    申请日:2013-03-14

    Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

    Abstract translation: 提供包括第一电介质层,第二电介质层,阻挡层和第二插塞的插塞结构。 其中具有第一插头的第一电介质层位于衬底上,其中第一插头物理地接触衬底中的源极/漏极。 具有暴露第一插头的开口的第二电介质层位于第一电介质层上。 阻挡层共形地覆盖开口,其中阻挡层具有底部部分和侧壁部分,并且底部部分是单层,并且在侧壁部分是双层的同时物理地接触第一插塞。 第二个塞子填充开口和阻挡层。 此外,还提供了形成插头结构的工艺。

    Two-portion shallow-trench isolation
    75.
    发明授权
    Two-portion shallow-trench isolation 有权
    两部分浅沟隔离

    公开(公告)号:US08823132B2

    公开(公告)日:2014-09-02

    申请号:US13736082

    申请日:2013-01-08

    Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

    Abstract translation: 提供浅沟槽隔离(STI)及其形成方法。 STI结构包括上绝缘部分和下绝缘部分,其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层,上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合,缓冲层的外侧壁和第一绝缘体的侧壁平整。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    76.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号:US20140183642A1

    公开(公告)日:2014-07-03

    申请号:US13728948

    申请日:2012-12-27

    Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

    Abstract translation: 半导体结构包括第一栅极和第二栅极,第一间隔物和第二间隔物,两个第一外延结构和两个第二外延结构。 第一栅极和第二栅极位于基板上。 第一间隔物和第二间隔物分别位于第一栅极和第二栅极旁边的衬底上。 第一外延结构和第二外延结构分别位于第一间隔物和第二间隔物旁边的衬底中,其中第一间隔物和第二间隔物具有不同的厚度,并且第一外延结构之间的间隔不同于 第二外延结构。 此外,本发明还提供了形成所述半导体结构的半导体工艺。

    Embedded resistor
    79.
    发明授权
    Embedded resistor 有权
    嵌入式电阻

    公开(公告)号:US09240403B2

    公开(公告)日:2016-01-19

    申请号:US13781761

    申请日:2013-03-01

    Abstract: An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer, or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench.

    Abstract translation: 提供了包括第一介电层,盖层,电阻层和盖膜的嵌入式电阻器。 第一介电层位于衬底上。 盖层位于第一介电层上,其中盖层具有沟槽。 电阻层共形地覆盖沟槽,从而具有U形横截面轮廓。 盖膜位于沟槽和电阻层中,或者提供包括第一介电层,盖层和体电阻层的嵌入式薄膜电阻器。 第一介电层位于衬底上。 盖层位于第一介电层上,其中盖层具有沟槽。 体电阻层位于沟槽中。

    Method for manufacturing semiconductor devices
    80.
    发明授权
    Method for manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号:US09196542B2

    公开(公告)日:2015-11-24

    申请号:US13899581

    申请日:2013-05-22

    Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

    Abstract translation: 提供一种制造半导体器件的方法。 形成第一堆叠结构和第二堆叠结构以分别覆盖第一鳍结构和第二鳍结构的一部分。 随后,通过原子层沉积工艺分别在翅片结构的侧壁上形成间隔物,间隔物的组成包括硅氮化硅。 之后,形成并蚀刻层间电介质,以露出硬掩模层。 形成掩模层以覆盖第二堆叠结构和介电层的一部分。 之后,在掩模层的覆盖下去除第一堆叠结构中的硬掩模层。 然后,第一堆叠结构中的虚设层被导电层代替。

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