中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

148 records (took 0.016 seconds)

    METHOD OF FORMING MEMORY CELL
    71.
    发明申请
    METHOD OF FORMING MEMORY CELL 有权

    公开(公告)号：US20210343789A1

    公开(公告)日：2021-11-04

    申请号：US17375021

    申请日：2021-07-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

    IPC: H01L27/24 ,  H01L27/28 ,  H01L45/00 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

    Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

    SEMICONDUCTOR DEVICE
    76.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200266095A1

    公开(公告)日：2020-08-20

    申请号：US16866360

    申请日：2020-05-04

    Applicant: United Microelectronics Corp.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

    INTERCONNECTION STRUCTURE AND METHOD OF FORMING THE SAME
    77.
    发明申请
    INTERCONNECTION STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20200258771A1

    公开(公告)日：2020-08-13

    申请号：US16858698

    申请日：2020-04-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

    IPC: H01L21/768 ,  H01L23/522

    Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.

    SEMICONDUCTOR DEVICE AND METHOD TO FABRICATE THE SEMICONDUCTOR DEVICE
    78.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD TO FABRICATE THE SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200185325A1

    公开(公告)日：2020-06-11

    申请号：US16212401

    申请日：2018-12-06

    Applicant: United Microelectronics Corp.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  San-Fu Lin

    IPC: H01L23/532 ,  H01L23/528 ,  H01L21/764 ,  H01L21/768

    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.

    Semiconductor structure and process thereof
    80.
    发明授权
    Semiconductor structure and process thereof 有权

    公开(公告)号：US10186453B2

    公开(公告)日：2019-01-22

    申请号：US14738943

    申请日：2015-06-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsin Liu ,  Bin-Siang Tsai

    IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/32 ,  H01L23/532 ,  H01L21/3105 ,  H01L23/485

    Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Patent Agency Ranking