公开(公告)号：US07749911B2

公开(公告)日：2010-07-06

申请号：US11001514

申请日：2004-11-30

申请人： Chung-Cheng Wu ,  Wen-Ting Chu

发明人： Chung-Cheng Wu ,  Wen-Ting Chu

IPC分类号： H01L21/311

CPC分类号： H01L21/28114 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/66575

摘要： A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

摘要翻译： 一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

公开(公告)号：US07683698B2

公开(公告)日：2010-03-23

申请号：US11841122

申请日：2007-08-20

申请人： Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Kuo-Wei Chu ,  Cheng-Hsiung Kuo ,  Jih-Chen Wang

发明人： Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Kuo-Wei Chu ,  Cheng-Hsiung Kuo ,  Jih-Chen Wang

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage.

摘要翻译： 提供一种电荷泵电路，其包括与具有用于接收输入电压的第一晶体管的前电荷泵级串联的至少两个电荷泵级，以及具有用于提供输出电压的第二晶体管的最后电荷泵级。 第一晶体管被配置为在第一阈值电压下操作，并且第二晶体管被配置为在不同于第一阈值电压的第二阈值电压下操作。

公开(公告)号：US07626224B2

公开(公告)日：2009-12-01

申请号：US11531295

申请日：2006-09-13

申请人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

发明人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/7881

摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

摘要翻译： 分离门存储单元。 第一和第二导电类型的第一和第二阱区域形成在衬底中。 浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。 控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分延伸到浮动栅极的上表面。 在第二阱区中形成第一导电类型的掺杂区域。 第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

公开(公告)号：US20090023255A1

公开(公告)日：2009-01-22

申请号：US11778558

申请日：2007-07-16

申请人： Yu-Hsiung Wang ,  Wen-Ting Chu ,  Eric Chen ,  Hsien-Wei Chin

发明人： Yu-Hsiung Wang ,  Wen-Ting Chu ,  Eric Chen ,  Hsien-Wei Chin

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/76224

摘要： A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.

摘要翻译： 提出了一种通过用牺牲层重塑硅表面来制造半导体器件的方法。 在本发明中，形成牺牲电介质层和去除牺牲电介质层的步骤被重复多次，以便从场氧化物附近的硅表面去除尖锐的边缘。 本发明的另一方面包括制造一种MOSFET晶体管，其将多个牺牲层的形成和去除结合到该工艺中。

公开(公告)号：US20080149985A1

公开(公告)日：2008-06-26

申请号：US11614677

申请日：2006-12-21

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

摘要翻译： 一种用于制造具有减小且更均匀的前向隧道电压的闪存单元的浮动栅极结构的改进方法。 该方法可以包括以下步骤：在衬底上形成至少两个浮动栅极; 在每个浮动栅极上形成掩模，每个掩模具有与给定厚度的相应一个浮动栅极的尖端相邻的部分，其中掩模部分的给定厚度彼此不同; 并且蚀刻掩模以将掩模部分的不同给定厚度减小到减小的厚度，其中掩模的厚度减小部分具有均匀的厚度。

公开(公告)号：US07297598B2

公开(公告)日：2007-11-20

申请号：US11045850

申请日：2005-01-28

申请人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Shih-Chi Fu ,  Chia-Ta Hsieh ,  Wen-Ting Chu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Shih-Chi Fu ,  Chia-Ta Hsieh ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.

摘要翻译： 一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域，其中第一掩模层在单元区域中具有多个开口。 在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域，然后可以去除第一掩模层。 可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅，其中蚀刻多晶硅层伴随着溅射。 然后可以形成电介质层，以及在电池区域和周边区域中形成第二掩模层。 在周边区域中的第二掩模层上形成光致抗蚀剂层之后，单元区域中的第二掩模层被部分地回蚀。 电介质层被部分蚀刻以形成介电层的多个厚度。 去除第二掩模层，并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

公开(公告)号：US07022592B2

公开(公告)日：2006-04-04

申请号：US10678783

申请日：2003-10-03

申请人： Wen-Ting Chu ,  Yeur-Luen Tu

发明人： Wen-Ting Chu ,  Yeur-Luen Tu

IPC分类号： H01L27/108

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： Semiconductor devices, and methods of fabricating, having ammonia-treated polysilicon devices are provided. A substrate is provided upon which a polysilicon layer is formed. The polysilicon layer is treated with ammonia. Thereafter, portions of the polysilicon layer may be oxidized, forming poly-oxide regions. The poly-oxide regions may be used, for example, to form the poly-oxide layer of a split-gate transistor. The ammonia treatment reduces the tendency of the polysilicon to oxidize along the grain boundaries, thereby allowing smaller designs to be fabricated without bridging occurring between polysilicon structures.

摘要翻译： 提供了具有氨处理的多晶硅器件的半导体器件和制造方法。 提供了形成多晶硅层的衬底。 用氨处理多晶硅层。 此后，多晶硅层的部分可能被氧化，形成多晶氧化物区域。 多晶氧化物区域例如可以用于形成分离栅极晶体管的多晶氧化物层。 氨处理降低了多晶硅沿着晶界氧化的趋势，从而允许制造较小的设计，而不会在多晶硅结构之间发生桥接。

公开(公告)号：US20050190595A1

公开(公告)日：2005-09-01

申请号：US10788949

申请日：2004-02-27

申请人： Wen-Ting Chu ,  Chia-Ta Hsieh

发明人： Wen-Ting Chu ,  Chia-Ta Hsieh

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： G11C16/10 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A split-gate, P-channel flash memory cell having a band-to-band hot electron (BBHE) programming method is defined to improve the endurance characteristics of performance of the cell. The split-gate, P-channel structure, which includes a P+ drain, P+ source, floating gate and a control gate, advantageously improves protection from over-erase and hot-hole trap conditions, and improves programming speed and higher injection efficiency. The cell is erased by a polysilicon-polysilicon tunneling technique.

摘要翻译： 定义了具有带 - 带热电子（BBHE）编程方法的分裂门P通道快闪存储器单元，以提高电池性能的耐久特性。 包括P +漏极，P +源极，浮动栅极和控制栅极的分离栅极P沟道结构有利地提高了对过度擦除和热阱阱条件的保护，并提高了编程速度和更高的注入效率。 电池被多晶硅多晶硅隧道技术擦除。

公开(公告)号：US20050184331A1

公开(公告)日：2005-08-25

申请号：US10786798

申请日：2004-02-25

申请人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

发明人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.

摘要翻译： 公开了一种用于防止反向隧道的分裂门闪存单元结构。 在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。 浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。 侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层， 浮栅绝缘体层。 栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。 导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

公开(公告)号：US20050133850A1

公开(公告)日：2005-06-23

申请号：US11051845

申请日：2005-02-03

申请人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/461

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.