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161 条记录 (耗时 0.036 秒)

    Liquid crystal display module
    71.
    发明授权
    Liquid crystal display module 有权
    液晶显示模块

    公开(公告)号：US07385664B2

    公开(公告)日：2008-06-10

    申请号：US10970662

    申请日：2004-10-22

    申请人： Joo-Hong Lee ,  Jae-Hyun Park

    发明人： Joo-Hong Lee ,  Jae-Hyun Park

    IPC分类号： G02F1/1345

    CPC分类号： G02F1/13452 ,  G02F1/133608 ,  G02F2202/22

    摘要： A liquid crystal display (LCD) module includes a liquid crystal panel, a backlight assembly to supply light to the liquid crystal panel, at least one first flexible film having first printed circuit patterns, a gate driving integrated circuit (IC) on the first flexible film, at least one ground pad on the first flexible film, and a top case electrically connected to the ground pad.

    摘要翻译： 液晶显示器（LCD）模块包括液晶面板，向液晶面板供应光的背光组件，具有第一印刷电路图案的至少一个第一柔性膜，第一柔性的栅极驱动集成电路（IC） 薄膜，第一柔性薄膜上的至少一个接地垫，以及电连接到接地垫的顶壳。

    Method of extracting low-frequency or high-frequency component from a signal with slope tracing waves
    73.
    发明申请
    Method of extracting low-frequency or high-frequency component from a signal with slope tracing waves 审中-公开
    从具有斜率跟踪波的信号中提取低频或高频分量的方法

    公开(公告)号：US20070232947A1

    公开(公告)日：2007-10-04

    申请号：US11701097

    申请日：2007-01-31

    申请人： Jung-Kuk Kim ,  Ki-Young Lee ,  Jae-Hyun Park ,  Min-Kyu Kim

    发明人： Jung-Kuk Kim ,  Ki-Young Lee ,  Jae-Hyun Park ,  Min-Kyu Kim

    IPC分类号： A61B5/04

    CPC分类号： A61B5/0452

    摘要： This invention is about extracting two signals from the signal in which more than two frequency components are mixed. In detail, this is about extracting low or high frequency component by distinguishing signal distortion using slope tracing wave. This invention applies two slope tracing wave to an arbitrary signal to track signal distortion and extract and remove low frequency component such as the variation of electrocardiogram signal baseline or easily extract or remove 60 Hz interference wave easily introduced to electrocardiogram. In addition, this allows easy detection of a specific waveform such as P wave and T wave from the electrocardiogram diagram by using the difference between the arbitrary signal and two slope tracing wave. The methods of this invention include distinguishing signal distortion, and detecting, extracting, removing the variation of unfavorable baseline using the shape characteristics of the distinguished section, and also detecting, extracting, removing external interference wave such as 60 Hz noise. In addition, the methods of this invention include distinguishing signal distortion and easily detecting P wave and T wave when the baseline is changed using the shape characteristics of the distinguished section.

    摘要翻译： 本发明涉及从其中混合两个以上频率分量的信号中提取两个信号。 详细地说，这是关于通过使用斜率跟踪波区分信号失真来提取低或高频分量。 本发明对任意信号应用两个斜率跟踪波跟踪信号失真，并提取和去除心电图信号基线变化等低频成分，或者容易地提取或去除容易引入心电图的60Hz干扰波。 此外，通过使用任意信号和两个斜率跟踪波之间的差异，这允许从心电图图容易地检测诸如P波和T波的特定波形。 本发明的方法包括使用识别部分的形状特征来区分信号失真和检测，提取，去除不利基线的变化，并且还检测，提取，去除诸如60Hz噪声的外部干扰波。 此外，本发明的方法包括区分信号失真并且使用识别部分的形状特征改变基线时容易地检测P波和T波。

    Floating gate, a nonvolatile memory device including the floating gate and method of fabricating the same
    74.
    发明申请
    Floating gate, a nonvolatile memory device including the floating gate and method of fabricating the same 审中-公开
    浮动栅极，包括浮动栅极的非易失性存储器件及其制造方法

    公开(公告)号：US20070200165A1

    公开(公告)日：2007-08-30

    申请号：US11656454

    申请日：2007-01-23

    申请人： Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Jung-Ho Moon ,  Soung-Youb Ha ,  Byeong-Cheol Lim

    发明人： Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Jung-Ho Moon ,  Soung-Youb Ha ,  Byeong-Cheol Lim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    摘要： Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.

    摘要翻译： 示例性实施例可以提供非易失性存储器件。 示例性实施例非易失性存储器件可以包括形成在半导体衬底上的浮置栅极结构，其间具有栅极绝缘层和/或与浮置栅极相邻形成的控制栅极，在它们之间具有隧道绝缘层。 浮置栅极可以包括形成在栅极绝缘层上的第一浮动栅极，形成在第一浮动栅极上的第二浮置栅极，其间具有第一绝缘图案，和/或形成在第一浮动栅极的至少一个侧壁上的栅极连接层 绝缘图案，使得栅极导电层可以电连接第一浮动栅极和第二浮动栅极。 第二浮栅可以在其纵向端形成有可能不接触栅极连接层的尖端。

    Method of fabricating a flash memory cell
    76.
    发明授权
    Method of fabricating a flash memory cell 有权
    制造闪存单元的方法

    公开(公告)号：US07205194B2

    公开(公告)日：2007-04-17

    申请号：US10874579

    申请日：2004-06-24

    申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

    摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

    摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same
    77.
    发明申请
    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same 有权
    具有多个有序区域的垂直位置的PRAM及其形成方法

    公开(公告)号：US20060076548A1

    公开(公告)日：2006-04-13

    申请号：US11246863

    申请日：2005-10-07

    申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    IPC分类号： H01L29/02

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

    摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

    摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device
    78.
    发明申请
    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
    具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法

    公开(公告)号：US20060027858A1

    公开(公告)日：2006-02-09

    申请号：US11246590

    申请日：2005-10-11

    申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

    摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

    摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。