Address buffer circuit and method for controlling the same
    71.
    发明授权
    Address buffer circuit and method for controlling the same 失效
    地址缓冲电路及其控制方法

    公开(公告)号:US07580318B2

    公开(公告)日:2009-08-25

    申请号:US11232175

    申请日:2005-09-21

    IPC分类号: G11C8/06 G11C5/14

    CPC分类号: G11C8/06

    摘要: An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in ‘no operation’ state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.

    摘要翻译: 一种用于半导体存储器件的地址缓冲器电路,其中地址缓冲器响应于控制信号的第一电平被使能(以输出内部地址信号),并且响应于控制信号的第二电平被禁止。 地址缓冲器控制单元在半导体存储器件不执行数据访问操作的“无操作”状态(NOP命令)中产生处于第二电平的控制信号,并且在半导体存储器件执行时产生处于第一电平的控制信号 数据访问操作,从而减少或最小化缓冲并由地址缓冲器输出的内部地址的输出,从而降低半导体存储器件的无操作状态期间的功耗。

    DIGITAL BROADCASTING TRANSMITTING/RECEIVING APPARATUS AND METHOD
    72.
    发明申请
    DIGITAL BROADCASTING TRANSMITTING/RECEIVING APPARATUS AND METHOD 审中-公开
    数字广播发送/接收设备和方法

    公开(公告)号:US20090040372A1

    公开(公告)日:2009-02-12

    申请号:US12112469

    申请日:2008-04-30

    IPC分类号: H04N7/12 H04N7/173

    摘要: Provided are a digital broadcasting transmitting/receiving apparatus and method. By converting content of a main-program to a stream, converting content of a sub-program forming a single digital broadcasting service through synchronization with the main-program by being subordinated to the main-program to a stream, generating program configuration information containing stream conversion information of the main-program and stream conversion information of the sub-program, multiplexing the converted main-program stream and the generated program configuration information and real-time transmitting the multiplexed signal, and transmitting the converted sub-program stream in non-real-time, various and new premium services with compatibility with existing digital broadcasting services can be provided to users.

    摘要翻译: 提供了一种数字广播发送/接收装置和方法。 通过将主程序的内容转换为流,通过从属于主程序的流程与主程序同步,将形成单个数字广播服务的子程序的内容转换为流,生成包含流程序的程序配置信息 子程序的主程序和流转换信息的转换信息,多路复用转换的主程序流和生成的程序配置信息,并实时发送多路复用信号,并将转换的子程序流发送到非程序流, 可以向用户提供与现有数字广播服务兼容的实时,多种和新的优质服务。

    Semiconductor memory devices having controllable input/output bit architectures
    73.
    发明授权
    Semiconductor memory devices having controllable input/output bit architectures 有权
    具有可控输入/输出位体系结构的半导体存储器件

    公开(公告)号:US07391634B2

    公开(公告)日:2008-06-24

    申请号:US11358798

    申请日:2006-02-21

    IPC分类号: G11C5/02 G11C5/06

    CPC分类号: G11C7/22

    摘要: A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.

    摘要翻译: 半导体存储器件可以包括半导体衬底,衬底上的第一单元存储器件和衬底上的第二单元存储器件。 第一单元存储器件可以被配置为响应于命令接收第一至第N个/或以上数据位和/或向外部设备提供第一至第N个/ 信号,地址信号和时钟信号,以及响应于第一芯片选择信号。 第二单元存储器件可以被配置为通过2N个第(N)个数据位接收(N + 1)个第个和/或提供(N + 1) 响应于命令信号,地址信号和时钟信号,以及响应于第二芯片选择信号,向外部设备提供/ SUP>至2N第数据位。 还讨论了相关方法。

    Transistor layout structures for controlling sizes of transistors without changing active regions, and methods of controlling the same
    74.
    发明申请
    Transistor layout structures for controlling sizes of transistors without changing active regions, and methods of controlling the same 失效
    用于控制晶体管尺寸而不改变有源区的晶体管布局结构及其控制方法

    公开(公告)号:US20080141204A1

    公开(公告)日:2008-06-12

    申请号:US12000056

    申请日:2007-12-07

    IPC分类号: G06F9/45

    CPC分类号: H01L27/088 H01L27/0207

    摘要: A structure for controlling the size of a transistor may include: an active region; a first gate line on the active region; one or more second gate lines on the active region; and source or drain regions arranged in three or more divided active regions that result from the first gate line and the one or more second gate lines dividing the active region into the divided active regions. A method of controlling the size of a transistor may include: arranging an active region; arranging a first gate line on the active region; arranging one or more second gate lines on the active region; arranging source or drain regions in three or more divided active regions; and controlling the size of the transistor by connecting to each other or separating from each other the source or drain regions using upper wires.

    摘要翻译: 用于控制晶体管尺寸的结构可以包括:有源区; 在活动区域​​上的第一个栅极线; 有源区上的一个或多个第二栅极线; 以及排列在三个或更多个分割的有源区域中的源极或漏极区域,其由第一栅极线和一个或多个第二栅极线分成有源区域分成有效区域。 控制晶体管尺寸的方法可以包括:布置有源区; 在活动区域​​上布置第一栅极线; 在所述有源区上布置一个或多个第二栅极线; 在三个或更多个分割的活性区域中排列源区或漏区; 以及通过使用上部导线彼此连接或彼此分离源极或漏极区域来控制晶体管的尺寸。

    Signaling method between MAC entities in a packet communication system
    75.
    发明授权
    Signaling method between MAC entities in a packet communication system 有权
    分组通信系统中MAC实体之间的信令方法

    公开(公告)号:US07359345B2

    公开(公告)日:2008-04-15

    申请号:US10225850

    申请日:2002-08-22

    IPC分类号: H04B7/212 H04Q7/00

    摘要: A signaling method between a MAC (Medium Access Control) layer entity of a transmission apparatus and a MAC layer entity of a reception apparatus in a packet communication system including the transmission apparatus and the reception apparatus wherein upon receiving a signaling request, the MAC layer entity of the transmission apparatus transmits a MAC signaling message including control information and a signaling indication indicating transmission of the control information and the MAC layer entity of the reception apparatus determines whether the MAC signaling message includes the signaling indication, and receives the control information included in the MAC signaling message, if the MAC signaling message includes the signaling indication.

    摘要翻译: 包括发送装置和接收装置的分组通信系统中的发送装置的MAC(介质访问控制)层实体与接收装置的MAC层实体之间的信令方法,其中,在接收到信令请求时,MAC层实体 发送包含控制信息的MAC信令消息和表示控制信息的发送的信令指示,接收装置的MAC层实体确定MAC信令消息是否包括信令指示,并且接收包含在该信令中的控制信息 MAC信令消息,如果MAC信令消息包括信令指示。

    Semiconductor memory device and arrangement method thereof
    76.
    发明授权
    Semiconductor memory device and arrangement method thereof 失效
    半导体存储器件及其布置方法

    公开(公告)号:US07295454B2

    公开(公告)日:2007-11-13

    申请号:US11225221

    申请日:2005-09-12

    IPC分类号: G11C5/06

    摘要: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

    摘要翻译: 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

    Apparatus and method for transmitting/receiving serving HS-SCCH set information in an HSDPA communication system
    77.
    发明授权
    Apparatus and method for transmitting/receiving serving HS-SCCH set information in an HSDPA communication system 失效
    在HSDPA通信系统中发送/接收服务HS-SCCH组信息的装置和方法

    公开(公告)号:US07283508B2

    公开(公告)日:2007-10-16

    申请号:US10359449

    申请日:2003-02-06

    IPC分类号: H04Q7/28

    CPC分类号: H04B7/2637 H04W72/0406

    摘要: A communication system includes a shared channel occupied by a plurality of user equipments (UEs) and spread with a plurality of channelization codes to transmit user data, and a plurality of control channels for transmitting control information related to the shared channel in order to enable the UEs to receive the shared channel signal. The system generates a plurality of control channel sets by classifying the control channels into a predetermined number of control channels, and assigns the control channel sets so that each of the UEs monitors a particular control channel set among the control channel sets. Upon detecting necessity to modify a control channel set to be assigned to a particular UE among the UEs, a Node B determines to modify a control channel set assigned into the UE to a new control channel set at a predetermined point of time to come. After determining to modify the control channel set, the Node B transmits an indicator indicating expected modification of the control channel set and information on the control channel set to be modified to the UE over a downlink.

    摘要翻译: 通信系统包括由多个用户设备(UE)占用的共享信道,并且利用多个信道化码进行传播以发送用户数据,以及用于发送与共享信道相关的控制信息的多个控制信道,以便能够 UE接收共享信道信号。 该系统通过将控制信道分类为预定数量的控制信道来生成多个控制信道集合,并且分配控制信道集合,使得每个UE监视控制信道集合中的特定控制信道集合。 在检测到需要修改在UE中分配给特定UE的控制信道时,节点B确定将分配给UE的控制信道集合修改为在预定时间点设置的新控制信道。 在确定修改控制信道集之后,节点B通过下行链路向UE发送指示控制信道集合的预期修改的指示符和关于要修改的UE的控制信道的信息。

    Layout structure of MOS transistors and methods of disposing MOS transistors on an active region
    78.
    发明申请
    Layout structure of MOS transistors and methods of disposing MOS transistors on an active region 失效
    MOS晶体管的布局结构和在有源区上设置MOS晶体管的方法

    公开(公告)号:US20070020858A1

    公开(公告)日:2007-01-25

    申请号:US11485341

    申请日:2006-07-13

    IPC分类号: H01L21/8234

    摘要: In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.

    摘要翻译: 在多个金属氧化物半导体(MOS)晶体管的布局结构中,布局结构可以包括具有第一漏极区域的第一组MOS晶体管和分别分配给与所有侧面隔离的组有源区域的第一源极区域 通过沟槽隔离,以及第二组MOS晶体管,其具有分配给组有源区的第二漏极区和第二源极区。 第二组布置在第一组与组有源区的边缘之间。 第一漏极区域和第一源极区域中的一个或两个不与指状栅电极的长度方向上的沟槽隔离边缘接触。

    Module for transferring PCB, apparatus for attaching PCB and liquid crystal display device including PCB
    79.
    发明申请
    Module for transferring PCB, apparatus for attaching PCB and liquid crystal display device including PCB 有权
    用于传输PCB的模块,用于连接PCB的装置和包括PCB的液晶显示装置

    公开(公告)号:US20060285946A1

    公开(公告)日:2006-12-21

    申请号:US11304014

    申请日:2005-12-14

    IPC分类号: B65H1/00

    摘要: A module for transferring a PCB including a first transfer body that is translatable along a first moving path to transfer a first PCB and a second transfer body that is translatable along a second moving path to transfer a second PCB with the second transfer body being formed with an aperture therein. Additionally the first transfer body is adjustable from a first position where the first transfer body does not fit through the aperture to a second position wherein the first transfer body can fit within the aperture.

    摘要翻译: 一种用于传送PCB的模块,其包括可沿着第一移动路径平移以传送第一PCB的第一传送体和可沿着第二移动路径平移的第二传送体,以便传送具有第二传送体的第二PCB, 其中的孔。 另外,第一传送体可从第一传送体不穿过孔的第一位置调节到第二位置,其中第一传送体可装配在孔内。