公开(公告)号：US20120269021A1

公开(公告)日：2012-10-25

申请号：US13535922

申请日：2012-06-28

申请人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

发明人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC分类号： G11C7/00

CPC分类号： G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

摘要翻译： 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US20100246239A1

公开(公告)日：2010-09-30

申请号：US12659840

申请日：2010-03-23

申请人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

发明人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

摘要翻译： 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US07534832B2

公开(公告)日：2009-05-19

申请号：US10505517

申请日：2002-12-26

申请人： Jeongheon Ahn ,  Seon-Hee Han ,  Kwang-Jin Lee

发明人： Jeongheon Ahn ,  Seon-Hee Han ,  Kwang-Jin Lee

IPC分类号： C08L53/00

CPC分类号： C08L55/02 ,  C08F257/02 ,  C08F265/04 ,  C08F265/06 ,  C08F265/08 ,  C08F285/00 ,  C08L27/06 ,  C08L51/003 ,  C08L51/04 ,  C08L67/02 ,  C08L69/00 ,  C08L2666/24 ,  C08L2666/02 ,  C08L2666/14 ,  C08L2666/04

摘要： The present invention relates to an acrylic impact modifier having a multilayered structure, which offers both superior impact resistance and coloring characteristics to engineering plastics, such as polycarbonate (PC) and a polycarbonate/polybutylene terephthalate alloy resin, or to a polyvinyl chloride resin. The present invention provides an acrylic impact modifier having a multilayered structure comprising: a) a seed prepared by emulsion copolymerization of a vinylic monomer and a hydrophilic monomer; b) a rubbery core surrounding the seed and comprising a C2 to C8 alkyl acrylate polymer, and c) a shell surrounding the rubbery core and comprising a C1, to C4 alkyl methacrylate polymer, a method for preparing the same, and a thermoplastic resin comprising the same.

摘要翻译： 本发明涉及一种具有多层结构的丙烯酸类抗冲击改性剂，其对工程塑料如聚碳酸酯（PC）和聚碳酸酯/聚对苯二甲酸丁二醇酯合成树脂或聚氯乙烯树脂具有优异的抗冲击性和着色特性。 本发明提供具有多层结构的丙烯酸类抗冲改性剂，其包含：a）通过乙烯基单体和亲水单体的乳液共聚制备的种子; b）包围种子并包含C 2至C 8烷基丙烯酸酯聚合物的橡胶芯，和c）包围橡胶芯并包含甲基丙烯酸C1-C4烷基酯聚合物的壳，其制备方法和包含 一样。

公开(公告)号：US06933758B2

公开(公告)日：2005-08-23

申请号：US10308453

申请日：2002-12-03

申请人： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

发明人： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

IPC分类号： G06F1/12 ,  G06F1/10 ,  H03K5/15 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

CPC分类号： H03L7/0814 ,  H03L7/087

摘要： A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

摘要翻译： 同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。 正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。 后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。 当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量 时钟信号。

公开(公告)号：US06735674B2

公开(公告)日：2004-05-11

申请号：US09886308

申请日：2001-06-21

申请人： Kwang-Jin Lee

发明人： Kwang-Jin Lee

IPC分类号： G06F1200

CPC分类号： G06F12/0846 ,  G06F13/1631

摘要： A method and device for maintaining data coherency in a semiconductor memory device, having two or more memory chips combined into one chip and operated according to a late select synchronous pipeline type input/output protocol. A method includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the memory chips and a normal read operation is performed through other read paths when all the comparison signals are same.

摘要翻译： 一种用于在半导体存储器件中维持数据一致性的方法和装置，具有组合成一个芯片并根据后期选择同步流水线类型输入/输出协议进行操作的两个或多个存储器芯片。 一种方法包括以下步骤：通过利用在最新写入操作中输入的芯片块选择地址信号和从最新写入地址和当前读取地址之间的比较获得的比较信号来产生第一和第二旁路加和信号; 以及通过利用第一和第二旁路加法信号和内部时钟信号产生具有彼此相反的逻辑值的第一和第二旁路控制信号，其中在与存储器芯片相关联的读取路径和正常读取中执行旁路操作 当所有比较信号相同时，通过其它读取路径执行操作。

公开(公告)号：US06459637B1

公开(公告)日：2002-10-01

申请号：US09895196

申请日：2001-06-29

申请人： Kwang-Jin Lee ,  Jong-Cheol Lee

发明人： Kwang-Jin Lee ,  Jong-Cheol Lee

IPC分类号： G11C700

CPC分类号： G11C29/02 ,  G11C7/06 ,  G11C7/1045 ,  G11C2207/2254

摘要： An apparatus for controlling an enable of a sense amplifier in a semiconductor memory device includes a test part for repeatedly varying a test code value until the enable of the sense amplifier has a zero margin with respect to data to be read by the sense amplifier, and for determining the test code value at a time point when the enable has the zero margin. A fuse array cuts a fuse corresponding to the determined test code value.

摘要翻译： 一种用于控制半导体存储器件中的读出放大器的使能的装置包括用于重复地改变测试代码值的测试部件，直到读出放大器的使能相对于读出放大器要读取的数据为止为止，以及 用于在启用具有零余量的时间点确定测试代码值。 保险丝阵列切断与确定的测试代码值对应的保险丝。

公开(公告)号：US6166969A

公开(公告)日：2000-12-26

申请号：US345582

申请日：1999-06-30

申请人： Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

发明人： Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/34 ,  H03K19/0185 ,  G11C7/00

CPC分类号： G11C7/06 ,  H03K19/018521

摘要： Disclosed is a level shifter that can receive and convert a first signal that can have various voltage logic levels to a second signal having internal voltage logic levels. The level shifter includes first and second ascending/descending circuits, where the first ascend/descending circuit receives the first signal and the second ascend/descending circuit receives an inverted first signal. Each ascend/descending circuit is operable to descend a high logic level of the received signal to a low output voltage level and ascend a low logic level of the received signal to a high output voltage level. The output voltages from the first and second ascending/descending circuits are input to a sense amplifier that amplifies the difference between the output voltages in order to generate the internal voltage logic levels of the second signal. The first and second ascending/descending circuits buffer their respective received signals using the high logic level of the input signal as a supply voltage. The same principles are also applicable to the level shifting from internal voltage logic levels to external voltage logic levels.

摘要翻译： 公开了一种电平转换器，其可以接收和转换可以具有各种电压逻辑电平的第一信号到具有内部电压逻辑电平的第二信号。 电平移位器包括第一和第二上升/下降电路，其中第一上升/下降电路接收第一信号，第二上升/下降电路接收反相的第一信号。 每个上升/下降电路可操作以将接收信号的高逻辑电平降低到低输出电压电平，并将接收信号的低逻辑电平上升到高输出电压电平。 来自第一和第二上升/下降电路的输出电压被输入到放大输出电压之间的差的读出放大器，以产生第二信号的内部电压逻辑电平。 第一和第二上升/下降电路使用输入信号的高逻辑电平作为电源电压来缓冲它们各自的接收信号。 相同的原理也适用于从内部电压逻辑电平转换到外部电压逻辑电平的电平。

公开(公告)号：US08980087B2

公开(公告)日：2015-03-17

申请号：US13141277

申请日：2009-12-22

申请人： Kwang-Jin Lee

发明人： Kwang-Jin Lee

IPC分类号： B01D61/18 ,  B01D61/22 ,  B01D61/20 ,  C02F1/44 ,  C02F1/00

CPC分类号： C02F1/44 ,  B01D61/18 ,  B01D61/20 ,  B01D61/22 ,  B01D65/02 ,  B01D2311/14 ,  B01D2315/06 ,  B01D2317/022 ,  B01D2317/04 ,  C02F2209/03 ,  C02F2303/20

摘要： A system and method for filtering is disclosed, which is capable of accomplishing a filtering operation at a high recovery rate of 96% or more, and realizing a compact and simplified system structure, the system comprising a water bath including an inlet and a discharging hole, wherein feed water to be treated is supplied to the inside of the water bath through the inlet, and concentrated water is discharged out through the discharging hole; and plural membrane cassettes including first and second membrane cassettes submerged into the feed water contained in the water bath, wherein the first membrane cassette is positioned nearest to the inlet, and the second membrane cassette is positioned nearest to the discharging hole, wherein the first membrane cassette treats the feed water with a first impurity concentration; the second membrane cassette treats the feed water with a second impurity concentration; and the first impurity concentration is smaller than the second impurity concentration.

摘要翻译： 公开了一种用于过滤的系统和方法，其能够以96％以上的高回收率实现过滤操作，并且实现了紧凑且简化的系统结构，该系统包括水浴，其包括入口和排出孔 其中待处理的给水通过入口供给到水浴的内部，并且浓缩的水通过排出孔排出; 以及多个膜盒，包括浸没在所述水浴中所含的给水中的第一和第二膜盒，其中所述第一膜盒位于最靠近所述入口的位置，所述第二膜盒位于最靠近所述排出孔的位置，其中所述第一膜 盒子以第一杂质浓度处理给水; 第二膜盒处理具有第二杂质浓度的给水; 并且第一杂质浓度小于第二杂质浓度。

公开(公告)号：US08974667B2

公开(公告)日：2015-03-10

申请号：US13376124

申请日：2010-06-03

申请人： Kwang-Jin Lee ,  Moo-Seok Lee ,  Yong-Cheol Shin

发明人： Kwang-Jin Lee ,  Moo-Seok Lee ,  Yong-Cheol Shin

IPC分类号： B01D63/02

CPC分类号： B01D63/022 ,  B01D63/021 ,  B01D2313/02 ,  B01D2313/21

摘要： A hollow fiber membrane module is disclosed, which is capable of preventing a bundle of hollow fiber membranes from being separated from a module case, the hollow fiber membrane module for accommodating a bundle of hollow fiber membranes closely held together through the use of potting agent, including a module case including: a first inner surface serving as a projection on which the bundle of hollow fiber membranes is stably placed; a second inner surface upwardly extending from one end of the first inner surface, the second inner surface including at least one separation-preventing groove to prevent the bundle of hollow fiber membranes from being separated from the module case; a third inner surface downwardly extending from the other end of the first inner surface; and a fourth inner surface connected to the third inner surface.

摘要翻译： 公开了一种中空纤维膜组件，其能够防止一束中空纤维膜与模块壳体分离，中空纤维膜组件用于容纳通过使用灌封剂紧密地保持在一起的一束中空纤维膜， 包括模块壳体，包括：第一内表面，用作其上稳定放置中空纤维膜束的突起; 从所述第一内表面的一端向上延伸的第二内表面，所述第二内表面包括至少一个分离防止槽，以防止所述中空纤维束束与所述模块壳体分离; 从所述第一内表面的另一端向下延伸的第三内表面; 以及连接到第三内表面的第四内表面。

公开(公告)号：US20130308370A1

公开(公告)日：2013-11-21

申请号：US13948138

申请日：2013-07-22

申请人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

发明人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC分类号： G11C13/00

CPC分类号： G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

摘要翻译： 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。