公开(公告)号：US6055199A

公开(公告)日：2000-04-25

申请号：US176880

申请日：1998-10-21

申请人： Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

发明人： Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

IPC分类号： G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401

摘要： A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.

摘要翻译： 用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路， 连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路 用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障， 电容器电介质，存储节点结等，从外部施加任意的应力电压 设备侧。

公开(公告)号：US6003148A

公开(公告)日：1999-12-14

申请号：US781387

申请日：1997-01-13

申请人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

发明人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/34 ,  G06F11/00

CPC分类号： G11C29/34

摘要： In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.

摘要翻译： 在预定的多位测试模式中，多位测试电路114将确定结果数据对RDM0和/ RDM0发送到RDM3和/ RDM3，每个RDM3和/ RDM3对应于从由一列选择线选择的存储器单元读取的数据的逻辑的匹配/不匹配 相应的一个存储单元平面块。 在每个存储单元平面块中，由单个列选择行选择的存储单元列可以被替换为单元。 根据确定结果数据RDM0和/ RDM0至RDM3和/ RDM3来替换包含有缺陷存储单元的存储单元列的单位。

公开(公告)号：US5732034A

公开(公告)日：1998-03-24

申请号：US759200

申请日：1996-12-04

申请人： Mikio Asakura ,  Tadaaki Yamauchi ,  Takashi Ito

发明人： Mikio Asakura ,  Tadaaki Yamauchi ,  Takashi Ito

IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00

CPC分类号： G11C29/46 ,  G11C8/06

摘要： An input first stage is used for inputting both addresses and address keys. A test mode setting circuit and a function setting circuit are disposed between the input first stage and an address buffer. Each function setting mode buffer latches an internal address signal when a signal/RAS falls. Further, a function signal generating circuit is initialized by a power-on reset signal when a power supply is turned on.

摘要翻译： 输入第一级用于输入地址和地址键。 测试模式设置电路和功能设置电路设置在输入第一级和地址缓冲器之间。 当信号/ RAS下降时，每个功能设置模式缓冲器锁存一个内部地址信号。 此外，当电源接通时，功能信号发生电路由上电复位信号初始化。

公开(公告)号：US5604710A

公开(公告)日：1997-02-18

申请号：US616734

申请日：1996-03-15

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C29/26 ,  G11C29/34 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C5/14 ,  G11C29/26 ,  G11C29/34 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10

摘要： Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supply voltage to data input/output pad portions, and power supply pad transmits the power supply voltage to data input/output pad portions. Power supply pad for peripheral circuitry is arranged in the center portion of the center region. A multibit test circuit is provided for each memory block. A data input/output buffer operating stably at high speed is implemented in a large storage capacity memory device which in turn accommodates a multibit test mode.

摘要翻译： 数据输入/输出焊盘部分对应于存储块并且与存储块和存储块之间的中心区域中相应的存储块相邻布置。 电源垫布置在中心区域的两端。 电源板将电源电压发送到数据输入/输出焊盘部分，电源焊盘将电源电压发送到数据输入/输出焊盘部分。 用于外围电路的电源板布置在中心区域的中心部分。 为每个存储块提供多位测试电路。 在大容量存储装置中实现高速稳定运行的数据输入/输出缓冲器，其又适应多位测试模式。

公开(公告)号：US5303183A

公开(公告)日：1994-04-12

申请号：US705812

申请日：1991-05-29

申请人： Mikio Asakura

发明人： Mikio Asakura

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/24

CPC分类号： G11C11/4074 ,  G11C11/404

摘要： In the case where information is read from a selected memory cell, the transfer gate included in the memory cell is turned on, and one electrode of the memory cell capacitor is connected to one bit line of a corresponding bit line pair. At the same time, the other electrode of the memory cell capacitor, i.e. the cell plate electrode is connected to the other bit line of the corresponding bit line pair. As a result, a change of the potentials occur at both the bit lines of the corresponding bit line pair. This change of the potentials acts in the different directions between one bit line and the other bit line. Therefore, the read potential difference appearing on the bit line pair becomes larger, and malfunction of the sense amplifier is reduced, while the incidence of soft error can be reduced.

摘要翻译： 在从所选存储单元读取信息的情况下，包含在存储单元中的传送门被接通，存储单元电容器的一个电极连接到相应位线对的一个位线。 同时，存储单元电容器的另一个电极，即单元板电极连接到相应位线对的另一个位线。 结果，在对应的位线对的位线的两端发生电位变化。 电位的这种变化在一个位线和另一个位线之间的不同方向上起作用。 因此，出现在位线对上的读取电位差变大，并且可以降低读出放大器的故障，同时可以降低软错误的发生。

公开(公告)号：US5226147A

公开(公告)日：1993-07-06

申请号：US564657

申请日：1990-08-09

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC分类号： G06F12/08 ,  G11C7/10

CPC分类号： G06F12/0893 ,  G11C7/1021

摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

公开(公告)号：US07032066B2

公开(公告)日：2006-04-18

申请号：US09956346

申请日：2001-09-20

申请人： Takeo Miki ,  Mikio Asakura ,  Takeshi Hamamoto

发明人： Takeo Miki ,  Mikio Asakura ,  Takeshi Hamamoto

IPC分类号： G11C7/10

CPC分类号： G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C11/4093

摘要： In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.

公开(公告)号：US06477105B2

公开(公告)日：2002-11-05

申请号：US10103698

申请日：2002-03-25

申请人： Kengo Aritomi ,  Mikio Asakura ,  Takashi Ito ,  Kiyohiro Furutani

发明人： Kengo Aritomi ,  Mikio Asakura ,  Takashi Ito ,  Kiyohiro Furutani

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C8/14

摘要： Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

摘要翻译： 要提供给子字线驱动器的互补子解码信号通过使用各个电源电压的不同电路分别产生。 因此，防止了在子字线驱动器中产生直通电流。

公开(公告)号：US06407942B2

公开(公告)日：2002-06-18

申请号：US09566488

申请日：2000-05-08

申请人： Kengo Aritomi ,  Mikio Asakura ,  Takashi Ito ,  Kiyohiro Furutani

发明人： Kengo Aritomi ,  Mikio Asakura ,  Takashi Ito ,  Kiyohiro Furutani

IPC分类号： G11C506

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C8/14

摘要： Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

公开(公告)号：US06327198B1

公开(公告)日：2001-12-04

申请号：US09500087

申请日：2000-02-08

申请人： Tetsuo Kato ,  Takayuki Miyamoto ,  Tetsushi Tanizaki ,  Mikio Asakura

发明人： Tetsuo Kato ,  Takayuki Miyamoto ,  Tetsushi Tanizaki ,  Mikio Asakura

IPC分类号： G11C2900

CPC分类号： G11C29/12

摘要： A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.

摘要翻译： 根据本发明的半导体存储器件包括：测试模式设置电路，能够根据外部信号串行设置多个测试模式; 电压发生电路; 列相关控制电路; 一行相关控制电路; 和存储单元阵列。 在对应的测试模式中，奇数字线/偶数字线被带入选择/非选择状态。 在相应的测试模式中，在正常操作模式下，位线的电压被设定为高于均衡电压（内部电源电压）或更低（接地电压）。 因此，可以有效地写入检查图案。