公开(公告)号：US09082695B2

公开(公告)日：2015-07-14

申请号：US13154346

申请日：2011-06-06

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L29/82 ,  H01L21/8246 ,  H01L43/12 ,  H01L27/115 ,  H01L27/22 ,  H01L43/08

CPC分类号： H01L27/222 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A method of manufacturing a magnetic memory cell, including a magnetic tunnel junction (MTJ), includes using silicon nitride layer and silicon oxide layer to form a trench for depositing copper to be employed for connecting the MTJ to other circuitry without the use of a via.

摘要翻译： 包括磁性隧道结（MTJ）的磁性存储单元的制造方法包括使用氮化硅层和氧化硅层形成用于沉积铜的沟槽，用于将MTJ连接到其它电路而不使用通孔 。

公开(公告)号：US09054298B2

公开(公告)日：2015-06-09

申请号：US13439817

申请日：2012-04-04

申请人： Yuchen Zhou ,  Yiming Huai

发明人： Yuchen Zhou ,  Yiming Huai

IPC分类号： H01L43/12 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  B82Y40/00

CPC分类号： H01L43/12 ,  B82Y40/00 ,  H01F10/3286 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/10

摘要： A spin transfer torque magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer. Cooling down the STTMRAM element to a second temperature that is lower than the first temperature and depositing a third free sub-layer directly on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.

公开(公告)号：US08971100B2

公开(公告)日：2015-03-03

申请号：US13546169

申请日：2012-07-11

申请人： Yuchen Zhou ,  Yiming Huai

发明人： Yuchen Zhou ,  Yiming Huai

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/161 ,  G11C11/5607 ,  G11C2013/0083 ,  Y10S977/933 ,  Y10S977/935

摘要： Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

摘要翻译： 描述了当所需的磁化方向为反平行时，使用外部产生的磁场序列来初始化用于数据和参考位的垂直MTJ MRAM元件中的每个层的磁化方向的方法。 可以使固定的固定和参考层的矫顽力不相等，使得它们中的一个可以通过可靠地离开另一个非磁性的磁场来切换。 本发明的实施例利用被钉扎，参考和自由层的不同有效矫顽力场，使用一系列降低强度的磁场来选择性地切换磁化方向。 可选地，可以加热芯片或晶片以减少所需的场强。 可以在MRAM制造过程中的退火步骤期间施加序列中的第一磁场。

公开(公告)号：US08806284B2

公开(公告)日：2014-08-12

申请号：US13462708

申请日：2012-05-02

申请人： Zihui Wang ,  Yuchen Zhou ,  Jing Zhang ,  Yiming Huai

发明人： Zihui Wang ,  Yuchen Zhou ,  Jing Zhang ,  Yiming Huai

IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/44

CPC分类号： G11C29/50008 ,  G11C11/16 ,  G11C13/00 ,  G11C29/08 ,  G11C29/44 ,  G11C29/50 ,  G11C29/56008 ,  G11C29/56016 ,  G11C2029/5602

摘要： A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected.

摘要翻译： 描述了一种测试方法，用于在晶片或芯片级上对基于电阻的RAM单元（如MTJ单元）执行快速误码率（BER）测量。 实施例使用一个或多个专门设计的测试存储单元，该测试存储单元通过电池的两个电极和晶片（或芯片）表面上的外部接触垫（或点）之间的直接电连接制造。 在测试设置中，存储单元通过探头连接阻抗不匹配的传输线，用于高电阻和低电阻状态之间的单元的非缓冲，快速切换，而不需要CMOS逻辑来选择和驱动单元。 使用不平衡传输线从电池产生作为电阻状态的函数的信号反射。 反射信号用于检测测试单元是否按预期切换。

公开(公告)号：US08796795B2

公开(公告)日：2014-08-05

申请号：US13136454

申请日：2011-08-01

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L45/00

CPC分类号： H01L27/222 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

摘要翻译： 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

公开(公告)号：US08772886B2

公开(公告)日：2014-07-08

申请号：US13099308

申请日：2011-05-02

申请人： Yiming Huai ,  Rajiv Yadav Ranjan ,  Ioan Tudosa ,  Roger Klas Malmhall ,  Yuchen Zhou

发明人： Yiming Huai ,  Rajiv Yadav Ranjan ,  Ioan Tudosa ,  Roger Klas Malmhall ,  Yuchen Zhou

IPC分类号： H01L29/82 ,  H01L43/10 ,  H01F10/32 ,  G11C11/16 ,  B82Y25/00 ,  H01L43/08 ,  H01L43/02

CPC分类号： H01L43/02 ,  B82Y25/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3295 ,  H01L43/08 ,  H01L43/10

摘要： A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a non-magnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.

摘要翻译： 自旋转矩存储器随机存取存储器（STTMRAM）元件能够在向其施加电流以存储数据时切换状态，并且包括以下层。 反铁磁层，形成在反铁磁层的顶部上的固定层，形成在固定层的第二磁性层顶部的阻挡层，以及形成在屏障顶部上的第一磁性层的自由层 形成在所述第一磁性层的顶部上的第二磁性层，形成在所述第二磁性层的顶部上的非磁性绝缘层和形成在所述非磁性绝缘层的顶部上的第三磁性层。 在非磁性绝缘层的顶部上形成覆盖层。

公开(公告)号：US08633720B2

公开(公告)日：2014-01-21

申请号：US13134925

申请日：2011-06-21

申请人： Ioan Tudosa ,  Yuchen Zhou ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Yiming Huai

发明人： Ioan Tudosa ,  Yuchen Zhou ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Yiming Huai

IPC分类号： G01R27/08

CPC分类号： G01R33/093

摘要： High-frequency resonance method is used to measure magnetic parameters of magnetic thin film stacks that show magnetoresistance including MTJs and giant magnetoresistance spin valves. The thin film sample can be unpatterned. Probe tips are electrically connected to the surface of the film (or alternatively one probe tip can be punched into the thin film stack) and voltage measurements are taken while injecting high frequency oscillating current between them to cause a change in electrical resistance when one of the layers in the magnetic film stack changes direction. A measured resonance curve can be determined from voltages at different current frequencies. The damping, related to the width of the resonance curve peak, is determined through curve fitting. In embodiments of the invention a variable magnetic field is also applied to vary the resonance frequency and extract the magnetic anisotropy and/or magnetic saturation of the magnetic layers.

摘要翻译： 高频共振法用于测量显示包括MTJs和巨磁阻自旋阀在内的磁阻的磁性薄膜叠层的磁参数。 薄膜样品可以无图案化。 探针尖端电连接到膜的表面（或者可选地，一个探针尖端可以冲压到薄膜堆叠中）并且在其间注入高频振荡电流时进行电压测量，以在其中的一个 磁膜堆中的层改变方向。 可以从不同电流频率的电压确定测得的谐振曲线。 通过曲线拟合确定与共振曲线峰的宽度相关的阻尼。 在本发明的实施例中，还应用可变磁场来改变谐振频率并提取磁性层的磁各向异性和/或磁饱和。

公开(公告)号：US20130267042A1

公开(公告)日：2013-10-10

申请号：US13443818

申请日：2012-04-10

申请人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

发明人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC分类号： H01L21/02

CPC分类号： H01L27/222 ,  H01L43/12

摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

摘要翻译： 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US08553452B2

公开(公告)日：2013-10-08

申请号：US13314470

申请日：2011-12-08

申请人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

发明人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/165

摘要： A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

摘要翻译： 描述了一种测试方法，其将具有不同强度的序列外部磁场施加到芯片或晶片中的MRAM单元（例如具有MTJ存储元件的那些），以选择性地筛选具有低或高热稳定性因子的单元。 矫顽力（Hc）用作热稳定因子（delta）的代表。 在各种实施例中，外部磁场的顺序，方向和强度用于确定不被正常场切换的高矫顽力单元以及通过选定的低场切换的低矫顽力单元。 在一些实施例中，MRAM的标准内部电流可用于切换电池。 可以使用标准的基于电路的电阻读取操作来确定每个单元对这些磁场的响应并识别异常的高和低矫顽力单元。

公开(公告)号：US08546151B2

公开(公告)日：2013-10-01

申请号：US12528854

申请日：2008-02-25

申请人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

发明人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

摘要： Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode. Also disclosed is a magnetic storage device comprising an interlayer insulating film provided with a wiring layer, an insulating film formed on the interlayer insulating film, an opening formed in the insulating film so that the wiring layer is exposed therefrom, a barrier metal layer provided so as to cover the inner surface of the opening, a lower electrode formed on the barrier metal so as to fill the opening, and a TMR element formed on the lower electrode.

摘要翻译： 公开了一种制造包括TMR元件的磁存储装置的方法，该方法包括在具有布线层的层间绝缘膜上形成绝缘膜的步骤，用于在绝缘膜上形成开口的开口形成步骤， 布线层暴露于其中，金属层形成步骤用于在绝缘层上形成金属层以使其开口被填充; CMP步骤，用于通过CMP方法在绝缘层上抛光和去除金属层，并形成金属 剩余在开口中的层形成下电极，以及在下电极上形成TMR元件的步骤。 还公开了一种磁存储装置，其包括设置有布线层的层间绝缘膜，形成在层间绝缘膜上的绝缘膜，形成在绝缘膜中的开口，使得布线层暴露于其中，阻挡金属层设置为 为了覆盖开口的内表面，形成在阻挡金属上以便填充开口的下电极和形成在下电极上的TMR元件。