公开(公告)号：US08704206B2

公开(公告)日：2014-04-22

申请号：US13356633

申请日：2012-01-23

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L29/06 ,  H01L47/00 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

摘要翻译： 本发明涉及其中结合有新颖的存储单元架构的存储器件，其包括共享公共通道的选择晶体管阵列及其制造方法。 存储器件包括具有第一类型导电性的半导体衬底，多个漏极区域和由衬底中的公共板沟道分开的公共源极区域，以及选择栅极，其设置在板沟道的顶部，栅极介电层插入 之间。 多个漏极区域和公共源极区域具有与设置在衬底中的第一类型相反的第二类型导电性。

公开(公告)号：US20120306005A1

公开(公告)日：2012-12-06

申请号：US13136051

申请日：2011-07-21

申请人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

发明人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： The present invention relates to transistor devices having a trough channel structure through which electrical current flows and methods for making the same. A transistor device having a semiconductor trough structure comprises a semiconductor substrate of a first conductivity type having a top surface; a semiconductor trough protruded from the top surface of the substrate along a first direction and having two top surfaces, two outer lateral surfaces, and an inner surface; a layer of isolation insulator disposed on the substrate and abutting the outer lateral surfaces of the semiconductor trough; a gate dielectric layer lining the inner surface and the top surfaces of the semiconductor trough; and a gate electrode disposed on top of the isolation insulator and extending over and filling the semiconductor trough with the gate dielectric layer interposed therebetween. The gate electrode extends along a second direction not parallel to the first direction provided in the semiconductor trough. Regions of the semiconductor trough not directly beneath the gate electrode have a second conductivity type opposite to the first conductivity type provided in the substrate.

摘要翻译： 本发明涉及具有通过电流流过的槽槽结构的晶体管器件及其制造方法。 具有半导体槽结构的晶体管器件包括具有顶表面的第一导电类型的半导体衬底; 半导体槽沿着第一方向从基板的顶表面突出并具有两个顶表面，两个外侧表面和内表面; 隔离绝缘层，设置在所述基板上并邻接所述半导体槽的外侧表面; 栅极电介质层，衬在半导体槽的内表面和顶表面上; 以及栅电极，其设置在隔离绝缘体的顶部并且延伸并填充半导体槽，栅介电层插入其间。 栅电极沿着不平行于半导体槽中的第一方向的第二方向延伸。 不直接在栅电极下方的半导体槽的区域具有与设置在基板中的第一导电类型相反的第二导电类型。

公开(公告)号：US20140042567A1

公开(公告)日：2014-02-13

申请号：US13572197

申请日：2012-08-10

申请人： Dong Ha Jung ,  Kimihiro Satoh ,  Jing Zhang ,  Yuchen Zhou ,  Yiming Huai

发明人： Dong Ha Jung ,  Kimihiro Satoh ,  Jing Zhang ,  Yuchen Zhou ,  Yiming Huai

IPC分类号： H01L43/12 ,  H01L43/02

CPC分类号： H01L43/12 ,  H01L43/08

摘要： Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.

摘要翻译： 描述了包括螺柱掩模和用于MTJ蚀刻以形成比MTJ柱的其余部分宽的底部电极的可移除间隔套的多层蚀刻掩模的使用。 所描述的本发明的第一实施例包括顶部电极和螺柱掩模。 在第二和第三实施例中，螺柱掩模是导电材料，并且还用作顶部电极。 在形成螺柱掩模之后的实施例中，在其周围形成间隔套，以最初增加蚀刻阶段的掩模宽度。 去除间隔物用于进一步蚀刻，以产生逐渐转移到形成MTJ柱的层中的阶梯结构。 在一个实施例中，间隔套筒是在蚀刻阶段期间通过净聚合物沉积形成的。

公开(公告)号：US08574928B2

公开(公告)日：2013-11-05

申请号：US13443818

申请日：2012-04-10

申请人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

发明人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC分类号： H01L21/00

CPC分类号： H01L27/222 ,  H01L43/12

摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

摘要翻译： 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US20130056698A1

公开(公告)日：2013-03-07

申请号：US13225431

申请日：2011-09-03

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/101 ,  H01L21/823487 ,  H01L27/105 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A resistive memory device comprises a semiconductor substrate having a first type conductivity; a plurality of vertical selection transistors formed on the semiconductor substrate in an array, each of the plurality of vertical selection transistors including a semiconductor pillar protruded from the semiconductor substrate, top region of the semiconductor pillar having a second type conductivity opposite to the first type conductivity provided in the semiconductor substrate; and a gate electrode surrounding the semiconductor pillar with a gate dielectric layer interposed therebetween, the gate electrode being lower in height than the semiconductor pillar; a plurality of contact studs disposed on top of the vertical selection transistors; a plurality of resistive memory elements disposed on top of the contact studs; a plurality of parallel word lines connecting the vertical selection transistors by way of respective gate electrodes, the parallel word lines extending along a first direction; a plurality of parallel bit lines connecting the resistive memory elements, the parallel bit lines extending along a second direction different from the first direction provided in the parallel word lines; and a plurality of parallel source lines with the second type conductivity formed in top regions of the semiconductor substrate in between rows of the semiconductor pillars, wherein the source lines and the top regions of the semiconductor pillars function as source and drain, respectively.

摘要翻译： 本发明涉及结合有垂直选择晶体管的电阻式存储器件及其制造方法。 电阻式存储器件包括具有第一类型导电性的半导体衬底; 多个垂直选择晶体管，形成在阵列中的半导体衬底上，多个垂直选择晶体管中的每一个包括从半导体衬底突出的半导体柱，半导体柱的顶部区域具有与第一类型导电性相反的第二类型导电性 设置在半导体衬底中; 以及围绕所述半导体柱的栅电极，其间插入有栅极电介质层，所述栅电极的高度低于所述半导体柱; 设置在垂直选择晶体管顶部的多个接触柱; 设置在接触柱顶部的多个电阻性存储元件; 多个并行字线，通过相应的栅电极连接垂直选择晶体管，并行字线沿着第一方向延伸; 连接所述电阻性存储器元件的多条并行位线，所述并行位线沿着与所述并行字线中设置的第一方向不同的第二方向延伸; 以及在半导体柱的行之间分别形成有在半导体衬底的顶部区域中的具有第二类型导电体的多条平行的源极线，其中半导体柱的源极线和顶部区域分别用作源极和漏极。

公开(公告)号：US09082695B2

公开(公告)日：2015-07-14

申请号：US13154346

申请日：2011-06-06

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L29/82 ,  H01L21/8246 ,  H01L43/12 ,  H01L27/115 ,  H01L27/22 ,  H01L43/08

CPC分类号： H01L27/222 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A method of manufacturing a magnetic memory cell, including a magnetic tunnel junction (MTJ), includes using silicon nitride layer and silicon oxide layer to form a trench for depositing copper to be employed for connecting the MTJ to other circuitry without the use of a via.

摘要翻译： 包括磁性隧道结（MTJ）的磁性存储单元的制造方法包括使用氮化硅层和氧化硅层形成用于沉积铜的沟槽，用于将MTJ连接到其它电路而不使用通孔 。

公开(公告)号：US08796795B2

公开(公告)日：2014-08-05

申请号：US13136454

申请日：2011-08-01

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L45/00

CPC分类号： H01L27/222 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

摘要翻译： 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

公开(公告)号：US20130267042A1

公开(公告)日：2013-10-10

申请号：US13443818

申请日：2012-04-10

申请人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

发明人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC分类号： H01L21/02

CPC分类号： H01L27/222 ,  H01L43/12

摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

摘要翻译： 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US20130052752A1

公开(公告)日：2013-02-28

申请号：US13199490

申请日：2011-08-30

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

IPC分类号： H01L21/8246

CPC分类号： H01L43/12 ,  H01L29/00

摘要： Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

摘要翻译： 本发明的各种实施例涉及用于制造MRAM装置中的MTJ电池的蚀刻工艺。 各种实施例可以彼此组合使用。 第一实施例在硬掩模和顶电极之间添加硬掩模缓冲层。 第二实施例使用多层蚀刻硬掩模。 第三实施例使用包括第二层如Ta之下的第一Cu层的多层顶电极结构。 第四实施例是用于底部电极去除再沉积材料同时保持更垂直侧壁蚀刻轮廓的两相蚀刻工艺。 在第一阶段中，使用碳质反应离子蚀刻去除底部电极层直到端点。 在第二阶段中，使用惰性气体和/或氧等离子体去除在先前蚀刻工艺期间沉积的聚合物。

公开(公告)号：US20130032907A1

公开(公告)日：2013-02-07

申请号：US13136454

申请日：2011-08-01

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.