利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

79 条记录 (耗时 0.063 秒)

    Semiconductor integrated circuit device having power reduction mechanism
    72.
    发明授权
    Semiconductor integrated circuit device having power reduction mechanism 失效
    具有功率降低机构的半导体集成电路装置

    公开(公告)号：US06404239B1

    公开(公告)日：2002-06-11

    申请号：US09613594

    申请日：2000-07-10

    申请人： Takayuki Kawahara ,  Ryoichi Hori ,  Masashi Horiguchi ,  Ryoichi Kurihara ,  Kiyoo Itoh ,  Masakazu Aoki ,  Takeshi Sakata ,  Kunio Uchiyama

    发明人： Takayuki Kawahara ,  Ryoichi Hori ,  Masashi Horiguchi ,  Ryoichi Kurihara ,  Kiyoo Itoh ,  Masakazu Aoki ,  Takeshi Sakata ,  Kunio Uchiyama

    IPC分类号： H03K1920

    CPC分类号： H03K3/356113 ,  H01L27/0218 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

    摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

    Purge control for ON-chip cache memory
    76.
    发明授权
    Purge control for ON-chip cache memory 失效
    片上高速缓存的清除控制

    公开(公告)号：US5809274A

    公开(公告)日：1998-09-15

    申请号：US886464

    申请日：1997-07-01

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F13/16 ,  G06F15/78

    CPC分类号： G06F9/30047 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824

    摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

    摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的指令作为输出。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。

    Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory
    77.
    发明授权
    Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory 失效
    具有片上高速缓冲存储器和清除控制器的数据处理器，响应于外部信号，用于控制对高速缓冲存储器的访问

    公开(公告)号：US5680631A

    公开(公告)日：1997-10-21

    申请号：US978069

    申请日：1992-11-18

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F13/16 ,  G06F15/78

    CPC分类号： G06F9/30047 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824

    摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

    摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器也有输出; 并且指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。

    Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses
    78.
    发明授权
    Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses 失效
    单芯片流水线处理器，用于根据其逻辑地址分别检测到的第一/第二命中/虚拟信号来提取/刷新指令/数据高速缓存

    公开(公告)号：US5206945A

    公开(公告)日：1993-04-27

    申请号：US606804

    申请日：1990-10-31

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3802 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/30047 ,  G06F9/3824

    摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

    摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有存储从主存储器读出的指令的第一关联存储器，以及指令控制单元，当指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。

    Data processor with on-chip logical addressing and off-chip physical addressing
    79.
    发明授权
    Data processor with on-chip logical addressing and off-chip physical addressing 失效
    具有片上逻辑寻址和片外物理寻址的数据处理器

    公开(公告)号：US5129075A

    公开(公告)日：1992-07-07

    申请号：US596751

    申请日：1990-10-12

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F13/16 ,  G06F15/78

    CPC分类号： G06F9/30047 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824

    摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and the instruction control unit also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory. The instruction controller provides the instruction to be executed as an output. The data processor further includes an instruction execution unit having a second associative memory storing operand data read out from the main memory, and an instruction execution unit that executes the instruction. The instruction execution unit uses operand data read out from the second associative memory when the operand data is present in the second associative memory and operand data from the main memory when the operand data is not present in the second associative memory.

    摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器，并且指令控制单元还包括指令控制器，其从第一 当指令存在于第一关联存储器中时，并且当指令不存在于第一关联存储器中时，与主存储器相关联的存储器。 指令控制器提供要作为输出执行的指令。 数据处理器还包括具有存储从主存储器读出的操作数数据的第二关联存储器的指令执行单元和执行该指令的指令执行单元。 当操作数数据存在于第二关联存储器中时，指令执行单元使用从第二关联存储器读出的操作数数据，当操作数数据不存在于第二关联存储器中时，来自主存储器的操作数数据。