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    Semiconductor memory device
    71.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07910975B2

    公开(公告)日：2011-03-22

    申请号：US10593275

    申请日：2005-06-03

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： H01L29/788 ,  H01L27/01 ,  H01L27/12

    CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

    摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

    摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

    SEMICONDUCTOR MEMORY DEVICE
    73.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20090070525A1

    公开(公告)日：2009-03-12

    申请号：US12268017

    申请日：2008-11-10

    申请人： Katsumi DOSAKA ,  Kazutami Arimoto ,  Kazunori Saito ,  Hideyuki Noda

    发明人： Katsumi DOSAKA ,  Kazutami Arimoto ,  Kazunori Saito ,  Hideyuki Noda

    IPC分类号： G06F12/00

    CPC分类号： G11C15/04 ,  G11C15/00

    摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.

    摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门 用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。 匹配线用作水平位线对或用于访问水平端口的信号线。 当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。 此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

    Semiconductor memory device
    74.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07480168B2

    公开(公告)日：2009-01-20

    申请号：US11819583

    申请日：2007-06-28

    申请人： Kazutami Arimoto ,  Hiroki Shimano

    发明人： Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C11/24

    CPC分类号： G11C7/18 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10882

    摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

    摘要翻译： 构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。 通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。 因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑并入的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

    Semiconductor memory device with row selection control circuit
    76.
    发明授权
    Semiconductor memory device with row selection control circuit 失效
    具有行选择控制电路的半导体存储器件

    公开(公告)号：US06909658B2

    公开(公告)日：2005-06-21

    申请号：US10842465

    申请日：2004-05-11

    申请人： Kazutami Arimoto ,  Hiroki Shimano

    发明人： Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2207/104

    摘要： A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.

    摘要翻译： 将自刷新定时器持续设置为使周期性地刷新请求信号FAY活动的操作状态。 当在刷新请求信号FAY和外部施加的读取/写入命令之间发生争用时，行选择相关电路/命令生成相关电路控制与行相关的控制信号，使得在例如读取或写入命令之后执行刷新操作 写操作结束。 子存储阵列SMA被划分为比常规情况更小的刷新周期，并且刷新周期在更短的时间段内结束。 因此，可以在读周期时间内完成读操作和刷新操作。 可以实现可以使用与SRAM的控制一样简单的DRAM内核。

    Semiconductor memory device
    77.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06781915B2

    公开(公告)日：2004-08-24

    申请号：US10274872

    申请日：2002-10-22

    申请人： Kazutami Arimoto ,  Hiroki Shimano

    发明人： Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C800

    CPC分类号： G11C7/18 ,  G11C11/405 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/108 ,  H01L27/10897

    摘要： Memory cells are arranged such that one-bit data is stored by two-bit memory cells. The cell plate electrode of the memory cell capacitor and the gate electrode of the memory cell transistor are formed in the same manufacturing step. The amplitude of an isolation control signal applied to a bit line isolation gate connecting the bit line and the sense amplifier is restricted, and the word line is driven according to a negative voltage non-boosted word line scheme. A well region where a memory block is formed and a well region where the isolation gate is formed are separately provided, and separate bias voltages are applied thereto. Thus, a DRAM (dynamic random access memory)-based logic merged memory is implemented without degrading dielectric breakdown characteristics of the gate insulating film.

    摘要翻译： 存储单元被布置成使得一位数据由两位存储器单元存储。 存储单元电容器的单元板电极和存储单元晶体管的栅极形成在相同的制造步骤中。 施加到连接位线和读出放大器的位线隔离栅的隔离控制信号的幅度受到限制，并且字线根据负电压非升压字线方案被驱动。 形成存储块的阱区和形成隔离栅的阱区分开设置，并且分别施加偏置电压。 因此，实现基于DRAM（动态随机存取存储器）的逻辑合并存储器而不降低栅极绝缘膜的绝缘击穿特性。

    Semiconductor memory device having row-related circuit operating at high speed
    79.
    发明授权
    Semiconductor memory device having row-related circuit operating at high speed 失效
    具有行相关电路的半导体存储器件以高速工作

    公开(公告)号：US06507532B1

    公开(公告)日：2003-01-14

    申请号：US09722687

    申请日：2000-11-28

    申请人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    发明人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    IPC分类号： G11C800

    CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C11/4087

    摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

    摘要翻译： 中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号 时钟周期，用于传输到每个存储器子块。 备用确定电路与时钟信号异步地执行备用确定。 可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

    Semiconductor merged logic and memory capable of preventing an increase in an abnormal current during power-up
    80.
    发明授权
    Semiconductor merged logic and memory capable of preventing an increase in an abnormal current during power-up 失效
    半导体合并逻辑和存储器能够防止上电期间异常电流的增加

    公开(公告)号：US06418075B2

    公开(公告)日：2002-07-09

    申请号：US09759315

    申请日：2001-01-16

    申请人： Hiroki Shimano ,  Kazutami Arimoto ,  Yasuhiro Ishizuka ,  Seizou Furubeppu ,  Hiroki Sugano

    发明人： Hiroki Shimano ,  Kazutami Arimoto ,  Yasuhiro Ishizuka ,  Seizou Furubeppu ,  Hiroki Sugano

    IPC分类号： G11C514

    CPC分类号： G11C5/145 ,  G11C5/14 ,  G11C5/147

    摘要： A semiconductor integrated circuit in which a logic and a memory are merged, includes a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory. The voltage generation unit includes a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages, and an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages. An activation control unit prevents the active unit from being activated until all of the plurality of external power supply voltages rise.

    摘要翻译： 其中逻辑和存储器被合并的半导体集成电路包括：电压产生单元，用于基于从电压产生单元的外部以不同的定时提供的两个或多个外部电源电压产生两个或多个内部电源电压， 将多个内部电源电压提供给存储器。 电压产生单元包括：始终激活的小电流馈送能力的待机单元，用于产生多个内部电源电压;以及具有大电流馈送能力的有源单元，其根据需要被激活，用于产生 多个内部电源电压。 激活控制单元防止有效单元在所有多个外部电源电压升高之前被激活。