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    Driver circuit with gate clamp supporting stress testing
    71.
    发明授权
    Driver circuit with gate clamp supporting stress testing 有权
    驱动电路与门夹支持压力测试

    公开(公告)号：US09490786B2

    公开(公告)日：2016-11-08

    申请号：US15088898

    申请日：2016-04-01

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ni Zeng

    IPC: H03B1/00 ,  H03K3/00 ,  H03K5/08 ,  H03K17/687

    CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

    Abstract: A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

    Abstract translation: 发电机电路被耦合以将控制信号施加到驱动输出节点的功率晶体管的栅极端子。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

    Image sensor device with aligned IR filter and dielectric layer and related methods
    72.
    发明授权
    Image sensor device with aligned IR filter and dielectric layer and related methods 有权
    具有对准IR滤光片和介电层的图像传感器器件及相关方法

    公开(公告)号：US09419047B2

    公开(公告)日：2016-08-16

    申请号：US14135743

    申请日：2013-12-20

    Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO., LTD.

    Inventor： Jing-En Luan

    IPC: H04N5/33 ,  H01L27/146 ,  H04N5/225

    CPC classification number: H01L27/14683 ,  H01L27/14618 ,  H01L2224/13 ,  H01L2224/73265 ,  H04N5/2254 ,  H04N5/2257

    Abstract: An image sensor device may include an interconnect layer, an image sensor IC adjacent the interconnect layer and having an image sensing surface, and a dielectric layer adjacent the image sensor IC and having an opening therein aligned with the image sensing surface. The image sensor device may also include an IR filter adjacent and aligned with the image sensing surface, and an encapsulation material adjacent the dielectric layer and laterally surrounding the IR filter.

    Abstract translation: 图像传感器装置可以包括互连层，邻近互连层并具有图像感测表面的图像传感器IC，以及邻近图像传感器IC的电介质层，并且具有与图像感测表面对准的开口。 图像传感器装置还可以包括与图像感测表面相邻并对齐的IR滤光器，以及邻近介电层并横向围绕IR滤光器的封装材料。

    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING
    73.
    发明申请
    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING 审中-公开
    带门夹的驱动电路支持应力测试

    公开(公告)号：US20160218700A1

    公开(公告)日：2016-07-28

    申请号：US15088898

    申请日：2016-04-01

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ni Zeng

    IPC: H03K5/08 ,  H03K17/687

    CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

    Abstract: A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

    Abstract translation: 发电机电路被耦合以将控制信号施加到驱动输出节点的功率晶体管的栅极端子。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

    Driver circuit with gate clamp supporting stress testing
    75.
    发明授权
    Driver circuit with gate clamp supporting stress testing 有权
    驱动电路与门夹支持压力测试

    公开(公告)号：US09331672B2

    公开(公告)日：2016-05-03

    申请号：US14449232

    申请日：2014-08-01

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Ni Zeng

    IPC: H03B1/00 ,  H03K3/00 ,  H03K3/011 ,  H03K17/687

    CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

    Abstract: A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

    Abstract translation: 发电机电路被耦合以施加驱动输出节点的功率晶体管的栅极端子的控制信号。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

    Methods and circuits to reduce pop noise in an audio device
    77.
    发明授权
    Methods and circuits to reduce pop noise in an audio device 有权
    减少音频设备弹奏噪音的方法和电路

    公开(公告)号：US09306523B2

    公开(公告)日：2016-04-05

    申请号：US14478531

    申请日：2014-09-05

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Ru Feng Du ,  Qi Yu Liu

    IPC: H04R3/00 ,  H03G3/34

    CPC classification number: H03F1/3205 ,  H03F1/0205 ,  H03F1/305 ,  H03F3/183 ,  H03F3/185 ,  H03F3/187 ,  H03F3/211 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/45179 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2203/21106 ,  H03F2203/45151 ,  H03F2203/45156 ,  H03G3/345 ,  H03G3/348 ,  H04R3/002

    Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

    Abstract translation: D类放大器接收和放大差分模拟信号，然后差分模拟信号被差分地积分。 两个脉冲宽度调制器产生对应于差分集成模拟信号的脉冲信号，两个功率单元产生输出脉冲信号。 功率单元的输出通过电阻反馈网络耦合到积分器的输入端。 模拟输出单元将脉冲信号转换为输出模拟信号。 差分积分电路实现静音/非静音之间的软转换。 静音时，积分器输出是固定的。 在软转换期间，PWM输出从固定的50％占空比缓慢变化到最终值，以确保由于模式更改而导致输出中没有弹出式噪声。

    Silent start class-D amplifier
    78.
    发明授权
    Silent start class-D amplifier 有权
    静音启动D类放大器

    公开(公告)号：US09231535B2

    公开(公告)日：2016-01-05

    申请号：US14199773

    申请日：2014-03-06

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Ru Feng Du ,  Qi Yu Liu

    IPC: H03F3/38 ,  H03F3/217

    CPC classification number: H03F3/2171 ,  H03F3/2175

    Abstract: A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no “pop” is introduced at start-up.

    Abstract translation: D类放大器包括前置放大器，其具有被配置为接收在启动时以快速速率斜坡的放大器参考电压信号的输入。 积分器具有被配置为从前置放大器接收输入信号的第一输入和被配置为接收以较慢速率在启动时斜坡上升的积分器参考电压信号的第二输入。 调制器具有耦合到积分器的输出的输入。 调制器产生脉宽调制输出信号。 通过将缓慢斜坡信号作为积分器参考电压信号和快速斜坡信号作为放大器参考电压来控制D类放大器的工作，使得脉宽调制输出信号在占空比上呈现增加的变化 响应于积分器参考电压信号的增加的电压，并且在启动时不引入“弹出”。

    POWER CONVERTER AND METHOD FOR REGULATING LINE TRANSIENT RESPONSE OF THE POWER CONVERTER
    79.
    发明申请
    POWER CONVERTER AND METHOD FOR REGULATING LINE TRANSIENT RESPONSE OF THE POWER CONVERTER 有权
    用于调节电力转换器的线路瞬态响应的功率转换器和方法

    公开(公告)号：US20150378378A1

    公开(公告)日：2015-12-31

    申请号：US14663165

    申请日：2015-03-19

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Hai Bo Zhang ,  Zi Yu Zeng ,  Jerry Huang

    IPC: G05F1/56

    CPC classification number: G05F1/56 ,  H02M1/4225 ,  H02M3/156 ,  H02M3/158 ,  H02M2001/0022

    Abstract: A power converter includes an input and an output with an energy storage circuit and a power switching circuit coupled between the input and the output. A feedback circuit generates a feedback voltage which is differentially compared to a reference in an error amplifier circuit to generate an error amplification signal. A comparator circuit generates a control signal for controlling on/off of the power switching circuit based on a first comparison signal related to the error amplification signal and a second comparison signal related to a charging current of the energy storage circuit. A regulating circuit is coupled between an output of the error amplifier circuit and an input of the comparator circuit for receiving the first comparison signal, the regulating circuit is configured to couple a voltage compensation signal related to an input voltage received by the input to an output of the error amplifier, so as to reduce a variation amount of the error amplification signal when the input voltage varies.

    Abstract translation: 功率转换器包括具有能量存储电路和耦合在输入和输出之间的功率开关电路的输入和输出。 反馈电路产生与误差放大器电路中的参考差分地相比较以产生误差放大信号的反馈电压。 比较器电路基于与误差放大信号相关的第一比较信号和与能量存储电路的充电电流相关的第二比较信号，产生用于控制功率开关电路的导通/截止的控制信号。 调节电路耦合在误差放大器电路的输出端和比较器电路的输入端之间，用于接收第一比较信号，调节电路被配置为将与输入接收的输入电压相关的电压补偿信号耦合到输出端 以便在输入电压变化时减小误差放大信号的变化量。

    Failure diagnosis circuit
    80.
    发明授权
    Failure diagnosis circuit 有权
    故障诊断电路

    公开(公告)号：US09076555B2

    公开(公告)日：2015-07-07

    申请号：US13597373

    申请日：2012-08-29

    Applicant: HongWei Wang ,  Luca Molinari

    Inventor： HongWei Wang ,  Luca Molinari

    IPC: G11C29/00 ,  G11C29/26 ,  G11C29/44 ,  G11C5/04

    CPC classification number: G11C29/18 ,  G11C5/04 ,  G11C7/00 ,  G11C8/00 ,  G11C29/26 ,  G11C29/44

    Abstract: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.

    Abstract translation: 故障诊断电路包括多路复用器和控制器。 多路复用器接收地址信号，并且响应于选择信号选择性地将一个地址信号输出到可寻址模块。 控制器产生第一个地址信号和选择信号。 内置的自检电路产生第二个地址信号。 可寻址模块包括响应于地址信号的可寻址组件。 控制器响应于地址信号处理可寻址模块的输出以进行故障诊断。 内置的自检电路对可寻址模块的读出输出执行签名分析。

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