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    Semiconductor chip including integrated circuit defined within dynamic array section
    71.
    发明授权
    Semiconductor chip including integrated circuit defined within dynamic array section 有权
    半导体芯片包括在动态阵列部分内定义的集成电路

    公开(公告)号：US09595515B2

    公开(公告)日：2017-03-14

    申请号：US14276528

    申请日：2014-05-13

    申请人： Tela Innovations, Inc.

    发明人： Scott T. Becker ,  Michael C. Smayling

    IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/118

    CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F2217/12 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2027/1182 ,  H01L2027/11866 ,  H01L2027/11874 ,  H01L2027/11888 ,  Y02P90/265

    摘要： A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing. The second and fourth ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a second end-to-end spacing substantially equal in size to the first end-to-end spacing.

    摘要翻译： 半导体芯片包括四个线性形状的导电结构，每个形成第一晶体管类型的对应晶体管的栅电极和第二晶体管类型的相应晶体管的栅电极。 四个线状导电结构中的第一和第二导电结构被定位成使其纵向取向的中心线由栅电极间距分开。 四个线状导电结构中的第三和第四个也被定位成使其纵向取向的中心线被栅电极间距分开。 四个线状导电结构中的第一和第三个被定位成使它们的长度方向取向的中心线共同对准并且被第一端到端间隔分开。 四个线性导电结构中的第二和第四个定位成使它们的长度方向取向的中心线共同对准并且被第二端对端间隔分开，第二端对端间隔的尺寸基本上等于第一端对端间隔 。

    Methods for cell boundary encroachment and layouts implementing the same
    72.
    发明授权
    Methods for cell boundary encroachment and layouts implementing the same 有权
    细胞边界侵入和布局实施方法

    公开(公告)号：US09269702B2

    公开(公告)日：2016-02-23

    申请号：US14187171

    申请日：2014-02-21

    申请人： Tela Innovations, Inc.

    发明人： Jonathan R. Quandt ,  Scott T. Becker ,  Dhrumil Gandhi

    IPC分类号： H01L27/02 ,  H01L27/118 ,  G06F17/50

    CPC分类号： H01L27/11803 ,  G06F17/5068 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

    摘要翻译： 公开了一种包括多个单元的半导体器件。 每个单元具有限定为以正交方式包围单元的相应外单元边界。 此外，每个单元包括用于执行一个或多个逻辑功能的电路。 该电路包括在单元的一个或多个层级中限定的多个导电特征。 给定单元的至少一个级别中的一个或多个导电特征是被定位成通过入侵距离侵入到禁区中的侵入特征。 排除区域占据由外部单元边界的第一段垂直向内延伸到给定单元格内的排除距离所限定的区域。 排除距离基于表示半导体器件上相邻放置的单元中的导电特征之间所需的最小间隔距离的设计规则距离。

    Enforcement of semiconductor structure regularity for localized transistors and interconnect
    73.
    发明授权
    Enforcement of semiconductor structure regularity for localized transistors and interconnect 有权
    局部晶体管和互连的半导体结构规范性的实施

    公开(公告)号：US09202779B2

    公开(公告)日：2015-12-01

    申请号：US14216891

    申请日：2014-03-17

    申请人： Tela Innovations, Inc.

    发明人： Stephen Kornachuk ,  Jim Mali ,  Carole Lambert ,  Scott T. Becker

    IPC分类号： G06F17/50 ,  H01L23/498

    CPC分类号： H01L23/528 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/12 ,  H01L23/498 ,  H01L23/5283 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    摘要： A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

    摘要翻译： 为芯片级定义全局放置光栅（GPG），以包括一组平行和均匀间隔的虚拟线。 GPG的至少一个虚拟线被定位成与与芯片级连接的每个触点相交。 定义了一些子格局。 每个子格局是GPG的一组等间距虚拟线，其支撑在其上的公共布局形状游程长度。 芯片级的布局被划分为子格局。 每个子格局区域具有分配给其中的任何一个限定的子格局。 放置在芯片级别的给定子格局区域内的布局形状根据分配给给定亚格局区域的子格局放置。 通过布局形状拉伸，布局形状插入和/或子分解形状插入可以减轻亚格子区域边界处的非标准布局形状间隔，或者可以允许存在于最终布局中。

    Super-self-aligned contacts and method for making the same
    76.
    发明授权
    Super-self-aligned contacts and method for making the same 有权
    超自对准触点及其制作方法

    公开(公告)号：US08951916B2

    公开(公告)日：2015-02-10

    申请号：US14033952

    申请日：2013-09-23

    申请人： Tela Innovations, Inc.

    发明人： Michael C. Smayling

    IPC分类号： H01L21/467 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/49

    CPC分类号： H01L27/092 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823828 ,  H01L23/481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

    摘要翻译： 多个第一硬掩模部分形成在电介质层上以垂直地遮蔽多个下面的栅极结构中的相应一个。 在每个第一硬掩模部分的每个侧表面附近形成多个第二硬掩模长丝。 将每个第二硬掩模灯丝的宽度设置为限定有源区域接触 - 栅极结构间隔。 在给定的一对相邻的第二硬掩模长丝的相对的暴露的侧表面之间蚀刻第一通道并且通过半导体晶片的深度到有源区域。 通过给定的第一硬掩模部分并通过半导体晶片的深度蚀刻第二通道到下面的栅极结构的顶表面。 导电材料沉积在第一和第二通道内，以分别形成有源区接触和栅极接触。

    Standard cells having transistors annotated for gate-length biasing
    78.
    发明授权
    Standard cells having transistors annotated for gate-length biasing 有权

    公开(公告)号：US08869094B2

    公开(公告)日：2014-10-21

    申请号：US13620683

    申请日：2012-09-14

    申请人： Puneet Gupta ,  Andrew B. Kahng

    发明人： Puneet Gupta ,  Andrew B. Kahng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

    摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

    Scalable meta-data objects
    79.
    发明授权
    Scalable meta-data objects 有权
    可扩展元数据对象

    公开(公告)号：US08839175B2

    公开(公告)日：2014-09-16

    申请号：US13312673

    申请日：2011-12-06

    申请人： Michael C. Smayling ,  Daryl Fox ,  Jonathan R. Quandt ,  Scott T. Becker

    发明人： Michael C. Smayling ,  Daryl Fox ,  Jonathan R. Quandt ,  Scott T. Becker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5077 ,  G06F2217/12 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/42376

    摘要： A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.

    摘要翻译： 公开了一种用于定义集成电路的方法。 该方法包括生成包括电连接信息和多个电路组件的物理拓扑信息的数字数据文件。 该方法还包括操作计算机以执行布局生成程序。 布局生成程序从数字数据文件中读取每个电路组件的电连接和物理拓扑信息，并自动创建在半导体器件制造工艺中形成每个电路部件数量所需的一个或多个布局结构， 使得一个或多个布局结构符合从数字数据文件读取的物理拓扑信息。 计算机还被操作来存储在计算机可读介质上以数字格式形成数个电路组件中的每一个所需的一个或多个布局结构。

    Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section
    80.
    发明申请
    Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section 审中-公开
    包含在动态阵列部分内定义的集成电路的半导体芯片

    公开(公告)号：US20140246733A1

    公开(公告)日：2014-09-04

    申请号：US14276528

    申请日：2014-05-13

    申请人： Tela Innovations, Inc.

    发明人： Scott T. Becker ,  Michael C. Smayling

    IPC分类号： H01L27/02

    CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F2217/12 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2027/1182 ,  H01L2027/11866 ,  H01L2027/11874 ,  H01L2027/11888 ,  Y02P90/265

    摘要： A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing. The second and fourth ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a second end-to-end spacing substantially equal in size to the first end-to-end spacing.

    摘要翻译： 半导体芯片包括四个线性形状的导电结构，每个形成第一晶体管类型的对应晶体管的栅电极和第二晶体管类型的相应晶体管的栅电极。 四个线状导电结构中的第一和第二导电结构被定位成使其纵向取向的中心线由栅电极间距分开。 四个线状导电结构中的第三和第四个也被定位成使其纵向取向的中心线被栅电极间距分开。 四个线状导电结构中的第一和第三个被定位成使它们的长度方向取向的中心线共同对准并且被第一端到端间隔分开。 四个线性导电结构中的第二和第四个定位成使它们的长度方向取向的中心线共同对准并且被第二端对端间隔分开，第二端对端间隔的尺寸基本上等于第一端对端间隔 。