公开(公告)号：US4187473A

公开(公告)日：1980-02-05

申请号：US903422

申请日：1978-05-08

Applicant: Michael J. Cochran

Inventor： Michael J. Cochran

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H03B3/04

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: An electronic phase locked loop circuit including a variable period sawtooth generator. The sawtooth generator receives digital reference clock signals and in response thereto generates sawtooth-shaped signals having the same period as said reference clock signals. A sample and hold circuit samples the sawtooth-shaped signals in response to one logical state of a sampling clock. A voltage controlled oscillator is coupled to the output of the sample and hold circuit and oscillates at a frequency proportional to the magnitude of the held sample. A feedback circuit generates the sampling clock by coupling the output of the voltage controlled oscillator to the sampling input of the sample and hold circuit.

Abstract translation: 一种包括可变周期锯齿波发生器的电子锁相环电路。 锯齿波发生器接收数字参考时钟信号，响应于此产生具有与所述参考时钟信号相同周期的锯齿形信号。 采样和保持电路响应于采样时钟的一个逻辑状态对锯齿形信号进行采样。 压控振荡器耦合到采样和保持电路的输出，并以与被保持的样本的幅度成正比的频率振荡。 反馈电路通过将压控振荡器的输出耦合到采样和保持电路的采样输入端产生采样时钟。

公开(公告)号：US4149128A

公开(公告)日：1979-04-10

申请号：US811748

申请日：1977-06-30

Applicant: James M. White

Inventor： James M. White

IPC: H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  H03H15/02 ,  H03H7/28 ,  G11C19/28 ,  H01L27/10 ,  H01L29/78

CPC classification number: H03H15/02 ,  H01L27/1057

Abstract: A charge transfer device transversal filter is provided having electronically controllable weighting factors. Two equivalent and corresponding charge transfer device shift registers have floating electrodes sandwiched between the sensing electrodes and the substrate for biasing the underlying depletion regions and thereby controlling the effective capacitances thereof. Depletion capacitances are controlled so as to produce desired weighting factors when corresponding and otherwise equal charging currents are substrated one from the other.

Abstract translation: 提供具有电子可控加权因子的电荷转移装置横向滤波器。 两个等效和相应的电荷转移装置移位寄存器具有夹在感测电极和衬底之间的漂浮电极，用于偏压下面的耗尽区，从而控制其有效电容。 控制耗尽电容，以便当相应的和相反的相等的充电电流彼此分开时产生所需的加权因子。

公开(公告)号：US4145675A

公开(公告)日：1979-03-20

申请号：US807530

申请日：1977-06-17

Applicant: Jean-Edgar Picquendar

Inventor： Jean-Edgar Picquendar

IPC: H03H15/02 ,  H03H7/28 ,  G11C19/28 ,  H01L27/10 ,  H03H7/10

CPC classification number: H03H15/02

Abstract: The invention relates to hybrid filters comprising a recursive part and a non-recursive part which make it possible to synthesize the filter by splitting the desired pass-band into two. It consists in using for the design of such a filter a charge-coupled device (CCD) in which these two parts are directly linked by a simple charge transfer mechanism without any other connection.

Abstract translation: 本发明涉及包括递归部分和非递归部分的混合滤波器，其使得可以通过将期望的通带分成两部分来合成滤波器。 它包括用于这种滤波器的设计，电荷耦合器件（CCD），其中这两个部分通过简单的电荷转移机制直接连接而没有任何其它连接。

公开(公告)号：US4145656A

公开(公告)日：1979-03-20

申请号：US791253

申请日：1977-04-27

Applicant: Jerry D. Merryman ,  Michael J. Cochran ,  Edward R. Caudel

Inventor： Jerry D. Merryman ,  Michael J. Cochran ,  Edward R. Caudel

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H04B1/38

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A transceiver receives electronic input signals comprised of a plurality of frequency bands lying within a plurality of non-overlapping frequency channels. A mixer frequency shifts a selected band to a predetermined center frequency in response to a first clocking signal of a first selectable frequency. A charge transfer device filter is coupled to the mixer output to filter the band of the predetermined center frequency in response to a second selectable frequency clocking signal. The clocking signals are generated by clocking means which receive digital microcommands identifying the selectable frequencies. Signal level measuring means are coupled to the output of the charge transfer device filter and generate digital level signals indicating the signal level present in the filtered band. Microprocessor means are coupled to send microcommands to the clocking means for sequentially filtering various channels from the plurality, and for monitoring the resulting digital level signals.

Abstract translation: 收发机接收由位于多个非重叠频率信道内的多个频带组成的电子输入信号。 混频器响应于第一可选择频率的第一时钟信号将所选频带移位到预定的中心频率。 电荷转移装置滤波器耦合到混频器输出端，以响应于第二可选频率时钟信号对预定中心频率的频带进行滤波。 时钟信号由接收识别可选择频率的数字微型命令的计时装置产生。 信号电平测量装置耦合到电荷转移装置滤波器的输出，并产生指示滤波频带中存在的信号电平的数字电平信号。 微处理器装置被耦合以将微指令发送到时钟装置，用于顺序地从多个通道中滤除各种通道，并用于监视所得到的数字电平信号。

公开(公告)号：US4137499A

公开(公告)日：1979-01-30

申请号：US791265

申请日：1977-04-27

Applicant: Edward R. Caudel

Inventor： Edward R. Caudel

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H04B17/00

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A transceiver includes an antenna having an input for transmitting electrical signals applied thereto. Signal generating means are provided for generating electrical reference signals of a fixed frequency. Transmission means selectively couple the reference signals to the antenna input in response to logic signals. Sensing means digitally indicate the forward voltage waveforms and reverse voltage waveforms on the antenna when the reference signals are applied thereto. A processor is coupled to selectively generate the logic signals and to receive the digital signals indicating the magnitude of the forward voltage and reverse voltage for making signal strength calculations thereon.

Abstract translation: 收发器包括具有用于发送施加到其上的电信号的输入的天线。 信号发生装置被提供用于产生固定频率的电参考信号。 传输装置响应于逻辑信号选择性地将参考信号耦合到天线输入端。 传感装置在将参考信号施加到其上时，数字地指示天线上的正向电压波形和反向电压波形。 耦合处理器以选择性地产生逻辑信号并且接收指示正向电压和反向电压的大小的数字信号，以在其上进行信号强度计算。

公开(公告)号：US4132951A

公开(公告)日：1979-01-02

申请号：US791254

申请日：1977-04-27

Applicant: Michael J. Cochran ,  Edward R. Caudel

Inventor： Michael J. Cochran ,  Edward R. Caudel

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H04B1/06

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A radio system includes a charge transfer device transversal filter for receiving electronic input signals comprised of at least one frequency band. The charge transfer device simultaneously receives a clocking signal, and filters and frequency shifts its input signals in response to the frequency of the clocking signal. Clocking means are provided for generating the clocking signal at frequencies as indicated in digital micro commands. A digital processor has outputs coupled to the clocking means for sending the micro commands to the clocking means.

公开(公告)号：US4126831A

公开(公告)日：1978-11-21

申请号：US791264

申请日：1977-04-27

Applicant: Michael J. Cochran

Inventor： Michael J. Cochran

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H03B3/04

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: An electronic phase detector circuit includes a variable period sawtooth generator. The sawtooth generator receives digital reference clock signals and in response thereto generates sawtooth-shaped signals having the same period as said reference clock signals. A sample and hold circuit samples the sawtooth-shaped signals in response to one logical state of a sampling clock. A voltage controlled oscillator is coupled to the output of the sample and hold circuit and oscillates at a frequency proportional to the magnitude of the held sample.

Abstract translation: 电子相位检测器电路包括可变周期锯齿波发生器。 锯齿波发生器接收数字参考时钟信号，响应于此产生具有与所述参考时钟信号相同周期的锯齿形信号。 采样和保持电路响应于采样时钟的一个逻辑状态对锯齿形信号进行采样。 压控振荡器耦合到采样和保持电路的输出，并以与被保持的样本的幅度成正比的频率振荡。

公开(公告)号：US4124861A

公开(公告)日：1978-11-07

申请号：US618747

申请日：1975-10-01

Applicant: Richard D. Baertsch ,  William E. Engeler

Inventor： Richard D. Baertsch ,  William E. Engeler

IPC: G11C19/28 ,  H01L29/768 ,  H03H15/02 ,  H01L29/78

CPC classification number: H03H15/02 ,  G11C19/282 ,  H01L29/76808 ,  H01L29/76866

Abstract: A charge transfer filter includes an accumulator charge storage location and means for alternately introducing charge into the accumulator charge storage location and then for removing a preselected fraction of the total charge in the accumulator charge storage location so that the total accumulated charge is known.

Abstract translation: 电荷转移滤波器包括蓄电池电荷存储位置和用于交替地将电荷引入蓄电池电荷存储位置中的装置，然后用于去除蓄电池电荷存储位置中的总电荷的预选部分，使得总累积电荷是已知的。

公开(公告)号：US4120035A

公开(公告)日：1978-10-10

申请号：US825123

申请日：1977-08-16

Applicant: Moises Cases ,  Fung Yuel Chang ,  Barry Jay Rubin

Inventor： Moises Cases ,  Fung Yuel Chang ,  Barry Jay Rubin

IPC: G06G7/16 ,  G11C27/04 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H03H15/02 ,  H03K5/159

CPC classification number: G11C27/04 ,  G06G7/16 ,  H01L29/76 ,  H03H15/02 ,  H03H2015/026

Abstract: A charge coupled device analog multiplier is used to weigh the sampled and delayed signals for a transversal filter. The digital filter coefficients for the analog multiplier can be electrically programmed and therefore dynamic time-varying systems, such as matched filters, can be designed with reduced circuit complexity. The digital filter includes means for sampling without destroying an analog signal at various points and providing voltages proportional to each sampled signal. The voltages are separately applied to a charge coupled device analog multiplier which accepts the voltages and provides means for multiplying the digital filter coefficient by the analog voltage. The multiplied sample signal is then dumped into a means for summing all of the weighted sample signals to produce an analog signal modified by the digital filter coefficients.

Abstract translation: 电荷耦合器件模拟乘法器用于对横向滤波器的采样和延迟信号进行称重。 模拟乘法器的数字滤波器系数可以进行电气编程，因此可以设计具有降低的电路复杂度的动态时变系统，例如匹配滤波器。 数字滤波器包括用于采样的装置，而不破坏各个点处的模拟信号并提供与每个采样信号成比例的电压。 电压分别施加到接收电压的电荷耦合器件模拟乘法器，并提供将数字滤波器系数乘以模拟电压的装置。 然后将相乘的采样信号转储成用于对所有加权采样信号求和的装置，以产生由数字滤波器系数修改的模拟信号。

公开(公告)号：US4107550A

公开(公告)日：1978-08-15

申请号：US760612

申请日：1977-01-19

Applicant: Christian A. Jacquart ,  Howard N. Leighton ,  Raymond J. Wilfinger

Inventor： Christian A. Jacquart ,  Howard N. Leighton ,  Raymond J. Wilfinger

IPC: G11C27/04 ,  B61L7/08 ,  G11C19/18 ,  G11C19/28 ,  G11C27/00 ,  H01L21/33 ,  H01L21/339 ,  H01L27/105 ,  H01L29/70 ,  H01L29/762 ,  H01L29/78 ,  H03H7/30 ,  H03H15/02 ,  H03M1/00 ,  G08C15/00 ,  G06G7/625 ,  G11C19/00 ,  H03K13/02

CPC classification number: H03H15/02 ,  B61L7/088 ,  G11C19/186 ,  G11C19/28 ,  G11C27/00 ,  H01L27/1055 ,  H01L29/78 ,  H03M1/76

Abstract: The underlying concept of the invention disclosed is the use of charge partitioning for providing a precision weighted tap in a bucket brigade circuit. At the drain node of a charge conducting element in a bucket brigade device, the signal path is split in half with a first half going to the source of a first FET and the second half going to the source of a second FET. The first and second FET devices have their associated overlap capacitances, transconductances and threshold voltages matched by virtue of their close proximity to one another on the semiconductor substrate so as to have matched charge transfer characteristics. The amplitude of the charge stored on the capacitor at the node is therefore divided into two parts, with one portion being transferred by the first FET device and the remaining portion being transferred by the second FET device. This simple circuit accomplishes a precise charge division for the charge entered into the bucket brigade circuit. Successive cells in the bucket brigade device can have their drain nodes connected to matched pairs of first and second FET devices to successively divide the charge stored therein by one-half so that a sequence of decrements in the charge transferred along the bucket brigade chain may be made in multiples of one-half. By selectively gating the outputs of each of the respective tapped branches from the bucket brigade device at a summing node, values of from zero to unity in fractional unit intervals can be generated as an analog output. A digital to analog converter may be formed by inputting a serialized digital word into the input of the bucket brigade device whose successive cells have attached thereto respective pairs of FET charge partitioning devices. The outputs of all branches are summed so that a resultant charge, which is the sum of the charges output by the charge partitioning transistors, will appear at the output as the analog value for the binary serial word input to the bucket brigade device.