公开(公告)号：US20120330873A1

公开(公告)日：2012-12-27

申请号：US13531226

申请日：2012-06-22

Applicant: Manan SURI ,  Barbara DE SALVO

Inventor： Manan SURI ,  Barbara DE SALVO

IPC: H03H11/26 ,  G06N3/04

CPC classification number: H01L45/06 ,  G06N3/049 ,  G06N3/0635 ,  H01L45/04 ,  H03K5/13 ,  H03K2005/00026 ,  H03K2005/00156

Abstract: A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.

Abstract translation: 延迟发生器包括由基于硫族化物的相变材料制成的至少一个可编程电阻器RPCM，所述电阻器RPCM被初始化，以便产生延迟，使得电阻器RPCM的电阻等于预设值 初始值R0，使得硫族化物处于非晶相，比较器将比较稳定的参考电量与表示可编程电阻器RPCM的电阻的可变电量比较，产生奇点信号s的比较器， 当两个电量之间的差异变化时，产生奇异点。

公开(公告)号：US08248135B2

公开(公告)日：2012-08-21

申请号：US12688084

申请日：2010-01-15

Applicant: Yue Yu ,  Han Bi

Inventor： Yue Yu ,  Han Bi

IPC: H03H11/26

CPC classification number: H04L25/0282 ,  H03K3/356034 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/0286 ,  H04L25/063

Abstract: A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a differential input pair (234), a latch stage (236) and a delay controller (244A1, 244A2, 244B1, 244B2). The delay controller (244A1, 244A2, 244B1, 244B2) selectively apportions current between the differential input pair (234) and the latch stage (236) to achieve a desired delay value for the circuit (10). The circuit (10) can also include a feedback loop (18) that calibrates a DC offset of the delay elements (22). The delay elements (22) can include two or more sets of resistive loads (238A, 238B) and a rate controller (241). The rate controller (241) controls an on/off state of the resistive loads (238A, 238B) to selectively switch between full resistance and half resistance. The rate controller (241) can also control the level of current (I1, I2) received by the differential input pair (234) and the latch stage (236) to control the delay value.

Abstract translation: 电路（10）包括电路输入（12），电路输出（16）和位于电路输入（12）和电路输出（16）之间的一个或多个延迟元件（22）。 延迟元件（22）各自包括差分输入对（234），锁存级（236）和延迟控制器（244A1,244A2,244B1,244B2）。 延迟控制器（244A1,244A2,244B1,244B2）选择性地分配差分输入对（234）和锁存级（236）之间的电流，以实现电路（10）的期望的延迟值。 电路（10）还可以包括校准延迟元件（22）的DC偏移的反馈回路（18）。 延迟元件（22）可以包括两组或更多组电阻性负载（238A，238B）和速率控制器（241）。 速率控制器（241）控制电阻负载（238A，238B）的开/关状态，以选择性地在全电阻和半电阻之间切换。 速率控制器（241）还可以控制由差分输入对（234）和锁存级（236）接收的电流（I1，I2）的电平以控制延迟值。

公开(公告)号：US20110175656A1

公开(公告)日：2011-07-21

申请号：US12688084

申请日：2010-01-15

Applicant: Yue Yu ,  Han Bi

Inventor： Yue Yu ,  Han Bi

IPC: H03L7/00

CPC classification number: H04L25/0282 ,  H03K3/356034 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/0286 ,  H04L25/063

Abstract: A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a differential input pair (234), a latch stage (236) and a delay controller (244A1, 244A2, 244B1, 244B2). The delay controller (244A1, 244A2, 244B1, 244B2) selectively apportions current between the differential input pair (234) and the latch stage (236) to achieve a desired delay value for the circuit (10). The circuit (10) can also include a feedback loop (18) that calibrates a DC offset of the delay elements (22). The delay elements (22) can include two or more sets of resistive loads (238A, 238B) and a rate controller (241). The rate controller (241) controls an on/off state of the resistive loads (238A, 238B) to selectively switch between full resistance and half resistance. The rate controller (241) can also control the level of current (I1, I2) received by the differential input pair (234) and the latch stage (236) to control the delay value.

Abstract translation: 电路（10）包括电路输入（12），电路输出（16）和位于电路输入（12）和电路输出（16）之间的一个或多个延迟元件（22）。 延迟元件（22）各自包括差分输入对（234），锁存级（236）和延迟控制器（244A1,244A2,244B1,244B2）。 延迟控制器（244A1,244A2,244B1,244B2）选择性地分配差分输入对（234）和锁存级（236）之间的电流，以实现电路（10）的期望的延迟值。 电路（10）还可以包括校准延迟元件（22）的DC偏移的反馈回路（18）。 延迟元件（22）可以包括两组或更多组电阻性负载（238A，238B）和速率控制器（241）。 速率控制器（241）控制电阻负载（238A，238B）的开/关状态，以选择性地在全电阻和半电阻之间切换。 速率控制器（241）还可以控制由差分输入对（234）和锁存级（236）接收的电流（I1，I2）的电平以控制延迟值。

公开(公告)号：US07893728B2

公开(公告)日：2011-02-22

申请号：US12289758

申请日：2008-11-03

Applicant: Kazunosuke Hirai

Inventor： Kazunosuke Hirai

IPC: H02M11/00 ,  H03F3/45

CPC classification number: H03K19/00361 ,  G05F3/24 ,  H03K3/0315 ,  H03K2005/00026 ,  H03K2005/00202

Abstract: An exemplary aspect of an embodiment of the present invention is a voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter including a first current generating circuit including an input transistor having a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor, and a second current generating circuit including a transistor having a gate having a potential different from potential of a source and a drain, the second current generating circuit generating a superimposed current according to the current flowing in the transistor to supply the superimposed current to the input transistor.

Abstract translation: 本发明的一个实施例的示例性方面是将输入到输入端的输入电压转换为电流以输出电流的电压 - 电流转换器，该电压 - 电流转换器包括第一电流产生电路，该第一电流产生电路包括具有 栅极连接到输入端子并根据在输入晶体管中流动的电流产生输出电流;以及第二电流产生电路，包括具有不同于源极和漏极的电位的栅极的晶体管，所述第二电流产生 电路根据在晶体管中流动的电流产生叠加电流，以将叠加的电流提供给输入晶体管。

公开(公告)号：US07826582B2

公开(公告)日：2010-11-02

申请号：US11523123

申请日：2006-09-18

Applicant: Mark D. Kuhns ,  Daniel L. Simon

Inventor： Mark D. Kuhns ,  Daniel L. Simon

IPC: H03D3/24 ,  H04L7/00 ,  H03L7/06 ,  H03L7/00

CPC classification number: H03K5/1565 ,  G06F1/025 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0805 ,  H03L7/0812

Abstract: A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

Abstract translation: 一种用于执行输出时钟相位平滑的系统和方法。 描述了相位平滑电路，并且包括被配置为以基于输入时钟的可选择频率产生多个NCO时钟脉冲的数控振荡器（NCO）。 多个NCO时钟脉冲的边缘与输入时钟的边缘对准。 相位误差计算模块耦合到NCO，并且被配置为针对多个NCO时钟脉冲中的每一个生成相应的相位误差。 时钟相位可选择延迟耦合到相位误差计算模块，并且被配置为根据相应的相位误差来调整多个NCO时钟脉冲中的每一个，以产生可选频率处的输出时钟，该输出时钟被相位调整以更紧密匹配 理想的输出时钟相位。 输出时钟的边沿不一定与输入时钟的边沿对齐。

公开(公告)号：US07812655B2

公开(公告)日：2010-10-12

申请号：US11973884

申请日：2007-10-09

Applicant: Harri Tapio Heinimäki

Inventor： Harri Tapio Heinimäki

IPC: H03L7/06 ,  H03K7/08

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0891

Abstract: This invention relates to devices, a chip, a method and a computer-readable medium for controlling operation of a delay-locked loop. A delay-locked loop unit is adapted to trigger generation of first-type edges of a target signal. A main control unit is adapted to control operation of the delay-locked loop unit in a way that the delay-locked loop unit is turned on before generation of each first-type edge of the target signal and turned off after generation of each first-type edge.

Abstract translation: 本发明涉及用于控制延迟锁定环路的操作的装置，芯片，方法和计算机可读介质。 延迟锁定环单元适于触发目标信号的第一类型边缘的产生。 主控制单元适于以延迟锁定环路单元在产生目标信号的每个第一类型边缘之前被导通并且在产生每个第一类型边缘之后被截止的方式来控制延迟锁定环单元的操作， 类型边缘。

公开(公告)号：US07777555B2

公开(公告)日：2010-08-17

申请号：US12360416

申请日：2009-01-27

Applicant: Chun-Yao Liao ,  Guan-Xing Huang ,  J-Ian Wu

Inventor： Chun-Yao Liao ,  Guan-Xing Huang ,  J-Ian Wu

IPC: H01L35/00

CPC classification number: G05F3/245 ,  H03K3/011 ,  H03K3/0315 ,  H03K2005/00026 ,  H03K2005/00143 ,  H03K2005/00202

Abstract: A temperature compensating circuit including a reference circuit, a transistor and a first circuit is provided. The reference circuit has a reference current and a resistance circuit, wherein the resistance circuit includes a first terminal receiving the reference current, a second terminal and a negative-temperature-coefficient resistor. The transistor has a drain, a source and a path disposed between the drain and the source, wherein the path of the transistor is connected in series with the resistance circuit, a gate of the transistor is electrically connected to the drain of the transistor and the second terminal of the resistance circuit, and the drain of the transistor produces a bias-voltage signal. The first circuit produces an output signal having a variable frequency in response to the bias-voltage signal, wherein the temperature compensating circuit utilizes the negative-temperature-coefficient resistor to compensate the variable frequency for a temperature change in the temperature compensating circuit.

Abstract translation: 提供了包括参考电路，晶体管和第一电路的温度补偿电路。 参考电路具有参考电流和电阻电路，其中电阻电路包括接收参考电流的第一端子，第二端子和负温度系数电阻器。 晶体管具有设置在漏极和源极之间的漏极，源极和路径，其中晶体管的路径与电阻电路串联连接，晶体管的栅极与晶体管的漏极电连接， 电阻电路的第二端子，晶体管的漏极产生偏置电压信号。 第一电路响应于偏置电压信号产生具有可变频率的输出信号，其中温度补偿电路利用负温度系数电阻器来补偿温度补偿电路中的温度变化的可变频率。

公开(公告)号：US07750706B1

公开(公告)日：2010-07-06

申请号：US11879080

申请日：2007-07-13

Applicant: Thomas B. Cho ,  Xiaoyue Wang

Inventor： Thomas B. Cho ,  Xiaoyue Wang

IPC: H03K3/289

CPC classification number: H03K5/13 ,  H03K2005/00026 ,  H03K2005/00097 ,  H03L7/0812

Abstract: Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ramp signal to a first threshold value in response to the reference clock signal to produce a comparison signal, a second ramp generator configured to produce a second ramp signal in response to the comparison signal, and a second comparison circuit configured to compare the second ramp signal to a second threshold value to produce the delayed clock signal.

Abstract translation: 用于产生延迟时钟信号的电路，系统和方法。 电路通常包括第一斜坡发生器，其被配置为响应于参考时钟信号产生第一斜坡信号，第一比较电路被配置为响应于参考时钟信号将第一斜坡信号与第一阈值进行比较以产生比较 信号，第二斜坡发生器，被配置为响应于所述比较信号产生第二斜坡信号;以及第二比较电路，被配置为将所述第二斜坡信号与第二阈值进行比较以产生所述延迟的时钟信号。

公开(公告)号：US07737795B2

公开(公告)日：2010-06-15

申请号：US11946932

申请日：2007-11-29

Applicant: Giri N. K. Rangan ,  Earl E. Swartzlander, Jr.

Inventor： Giri N. K. Rangan ,  Earl E. Swartzlander, Jr.

IPC: H03K3/03 ,  H03H11/26

CPC classification number: H03K3/0322 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03K2005/00234

Abstract: A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.

Abstract translation: 公开了一种基于环形振荡器的压控振荡器（VCO）。 VCO包括以环形配置彼此连接的一组延迟单元。 每个延迟单元包括源极耦合输入晶体管对，导流晶体管对和一对负载电阻。 源极耦合输入晶体管对接收一对差分电压输入。 连接到源极耦合输入晶体管对的负载电阻提供一对差分电压输出。 连接到源极耦合输入晶体管对的导流晶体管对接收一对差分偏置电压输入。 VCO的输出频率与差分偏置电压输入对的差分偏置电压成正比。

公开(公告)号：US20100134162A1

公开(公告)日：2010-06-03

申请号：US12606666

申请日：2009-10-27

Applicant: Masafumi KONDOU

Inventor： Masafumi KONDOU

IPC: H03L7/06 ,  H03K3/03

CPC classification number: H03L7/0995 ,  G01R31/31727 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1504 ,  H03K2005/00026 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0996

Abstract: A clock signal generation apparatus includes a clock signal generation circuit generating a plurality of clock signals, and a self-test circuit measuring a phase difference of one pair of clock signals. The self-test circuit includes a clock signal selection circuit selecting the pair of clock signals among the plurality of clock signals, a phase detection circuit generating a phase difference pulse signal, a test signal generation circuit generating a test signal having a frequency which is lower than the phase difference pulse signal, and a counter circuit counting the pulse number of the test signal.

Abstract translation: 时钟信号发生装置包括产生多个时钟信号的时钟信号产生电路和测量一对时钟信号的相位差的自检电路。 自检电路包括选择多个时钟信号中的一对时钟信号的时钟信号选择电路，产生相位差脉冲信号的相位检测电路，产生频率较低的测试信号的测试信号产生电路 比相位差脉冲信号，以及对测试信号的脉冲数进行计数的计数电路。