公开(公告)号：US5773344A

公开(公告)日：1998-06-30

申请号：US646993

申请日：1996-05-09

Applicant: Fumitomo Matsuoka ,  Yukari Unno

Inventor： Fumitomo Matsuoka ,  Yukari Unno

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/52 ,  H01L23/522 ,  H01L27/092 ,  H01L27/11 ,  H01L21/336 ,  H01L21/4763

CPC classification number: H01L21/76886 ,  H01L21/823871 ,  H01L27/11 ,  H01L2924/0002 ,  Y10S257/903 ,  Y10S257/904

Abstract: A polycrystalline silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the polycrystalline silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polycide gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten silicide layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten silicide layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten silicide layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer. In the manufacturing method as described above, an ohmic contact can be realized between the polycide gate electrode and the diffusion layer via the tungsten silicide layer, irrespective of the conductivity types of the gate electrode and the diffusion layer, without use of any additional metallic layer other than the polycide.

Abstract translation: 通过氧化膜在N型硅衬底上形成多晶硅层。 通过施加光致抗蚀剂掩模，并且进一步通过图案化多晶硅栅极和扩散层之间的预定接触部分，在多晶硅层上形成接触孔。 此后，通过使用相同的光致抗蚀剂掩模的离子注入形成P +扩散层。 此外，在整个衬底上沉积硅化钨层。 否则，在形成接触孔之后，沉积硅化钨层，然后通过离子注入形成P +扩散层。 或者，在形成接触孔之后，进行第一离子注入; 在沉积硅化钨层之后，进行第二离子注入以形成P +扩散层。 在如上所述的制造方法中，不管栅电极和扩散层的导电类型如何，都可以通过硅化钨层在多晶硅栅极电极和扩散层之间实现欧姆接触，而不使用任何额外的金属层 除了多杀菌剂。

公开(公告)号：US5757053A

公开(公告)日：1998-05-26

申请号：US595609

申请日：1996-04-19

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/02 ,  H01L29/76

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S257/904

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract translation: 在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的器件和方法包括在半导体衬底上形成第一多晶硅层，对第一多晶硅含量层进行图案化和蚀刻以在两侧形成步骤 在所述第一多晶硅含硅层上形成电介质层，所述第一多晶硅含有层的任一侧上具有台阶，形成在所述多晶硅层上延伸的第二多晶硅含量层的覆盖层，以及离子注入所述第二多晶硅 包含光剂量的掺杂剂的包覆层植入物，其包括在步骤上的区域中具有远高于电阻率的离子注入电阻区域。

公开(公告)号：US5751043A

公开(公告)日：1998-05-12

申请号：US823572

申请日：1997-03-25

Applicant: Chue-San You

Inventor： Chue-San You

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904

Abstract: A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolysilicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.

Abstract translation: 在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的方法包括在所述半导体衬底上形成多晶硅1层。 多晶硅1层被图案化和蚀刻。 在多晶硅1层上形成多晶硅层，经图案化和蚀刻，形成通过多晶硅层的开口，暴露多晶硅1层表面上的接触区域。 SIPOS层在通过开口与多晶硅1层接触的多晶硅层上形成电阻材料。 在要形成在SIPOS层中的负载电阻器区域上形成负载电阻器掩模，并且将离子注入到不被负载电阻器掩模覆盖的SIPOS层的其余部分中，以将SIPOS层的其余部分从电阻器转换成 互连结构与负载电阻器区域中的负载电阻器成一体。

公开(公告)号：US5732023A

公开(公告)日：1998-03-24

申请号：US815300

申请日：1997-03-11

Applicant: Ceredig Roberts

Inventor： Ceredig Roberts

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates. In an additional aspect, an SRAM cell having at least four field effect transistors includes, i) at least four transistor gates, an electrical interconnect line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and ii) the Vcc line and the electrical interconnect line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

公开(公告)号：US5710449A

公开(公告)日：1998-01-20

申请号：US651231

申请日：1996-05-22

Applicant: Chuen-Der Lien ,  Pailu D. Wang

Inventor： Chuen-Der Lien ,  Pailu D. Wang

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/0847 ,  H01L27/1104 ,  H01L29/7833 ,  Y10S257/903 ,  Y10S257/904

Abstract: Lightly doped active regions in a semiconductor structure reduce occurrences of pipeline defects. The light doped active region are typically employed where performance is not adversely affected. For example, in memory cells, pass transistors have lightly doped drains which directly connect to bit lines. A pass transistor of this type can have the source more heavily doped than the drain. Alternatively, drains and sources of pass transistors are lightly doped. Drains of pull-down transistors can also be lightly doped. The difference in doping of active regions does not increase fabrication processing steps because conventionally active regions are formed by two doping steps to create a lightly doped portions adjacent gates where field strength is highest. The invention changes such processes by covering the desired lightly active regions with the mask used during a second doping process.

公开(公告)号：US5683930A

公开(公告)日：1997-11-04

申请号：US568173

申请日：1995-12-06

Applicant: Shubneesh Batra ,  Monte Manning

Inventor： Shubneesh Batra ,  Monte Manning

IPC: H01L21/8244 ,  H01L27/06 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L27/11 ,  H01L27/0688 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S438/918 ,  Y10S438/947

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down gate diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the resistor nodes; d) providing a pair of contact openings, with respective widths, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating annulus spacers received within the respective pair of contact openings and a pair of elongated pull-up resistor openings laterally inward thereof; g) providing electrically conductive material within the pair of elongated pull-up resistor openings in electrical connection with the pair of pull-up resistor nodes to define the pull-up resistors; and h) providing a Vcc line in electrical connection with the pull-up resistors. SRAM circuitry produced according to the above method and by other methods are also contemplated.

Abstract translation: 一种形成SRAM单元的方法包括：a）提供一对具有与其可操作相邻的相关联的晶体管扩散区的下拉栅极，每个下拉栅极的扩散区域之一电连接到另一个下拉栅极; b）提供一对上拉电阻器节点，用于与一对相应的上拉电阻器电连接，所述上拉节点与下拉栅极扩散区域中的一个和另一个下拉电阻器分别电连接 门; c）在所述电阻器节点之外提供第一电绝缘层; d）提供一对具有相应宽度的接触开口，穿过第一绝缘层到一对电阻器节点; e）在所述第一层之上和所述一对接触开口内设置第二电绝缘层，其厚度小于所述开口宽度的一半; f）各向异性蚀刻第二电绝缘层以限定容纳在相应的一对接触开口内的相应的电绝缘环形间隔件和一对横向向内的细长的上拉电阻器开口; g）在所述一对细长上拉电阻器开口内提供与所述一对上拉电阻器节点电连接的导电材料，以限定所述上拉电阻器; 和h）提供与上拉电阻器电连接的Vcc线。 还考虑了根据上述方法和其它方法生产的SRAM电路。

公开(公告)号：US5672536A

公开(公告)日：1997-09-30

申请号：US657300

申请日：1996-06-03

Applicant: Jeff Zhiqiang Wu ,  Joseph Karniewicz

Inventor： Jeff Zhiqiang Wu ,  Joseph Karniewicz

IPC: H01L21/8244 ,  H01L21/8246 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/11266 ,  H01L27/11 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S438/979

Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

Abstract translation: 具有不超过三个晶体管的静态存储单元。 通过提供半导体衬底形成静态存储单元; 在衬底中形成掩埋的n型层，n型层具有至少1×10 16个离子/ cm 3的第一平均n型掺杂剂浓度; 在所述掩埋的n型层上形成相对于所述衬底的n沟道晶体管，所述n沟道晶体管具有源极，栅极和漏极，所述源极具有至少1×1019个离子的第二平均n型掺杂剂浓度 并且所述漏极具有至少1×1019个离子/ cm 3的第三平均n型掺杂剂浓度，并且所述源的深度比所述漏极深，以便比所述漏极更接近所述掩埋的n型层; 以及在与源极连接处形成p型区域以在p型区域和源极之间限定隧道二极管。

公开(公告)号：US5661325A

公开(公告)日：1997-08-26

申请号：US508986

申请日：1995-07-28

Applicant: Taketoshi Hayashi ,  Ryuzo Tagami

Inventor： Taketoshi Hayashi ,  Ryuzo Tagami

IPC: H01L27/11 ,  H01L29/76 ,  H01L29/00

CPC classification number: H01L27/1112 ,  Y10S257/904

Abstract: In a semiconductor device, an undoped polysilicon layer on the uppermost layer is used as a resistor having a high resistance without any patterning. A metal wiring layer formed on this resistor is connected to a conductive layer formed below the resistor via a contact hole extending through the high resistor device. In addition, by oxidizing an end portion, exposed in the contact hole, of the resistor, an oxide film is interposed between the high resistor device and the metal wiring layer to attain electrical insulation therebetween. In this manner, the resistor is formed of the undoped polysilicon layer by using a multilayered polysilicon structure including the undoped polysilicon layer. Therefore, the integration degree can be increased, and at the same time, a stepped portion accompanying the multilayered silicon structure is relaxed to improve the flatness of the surface and prevent poor step coverage or bridging of an upper wiring layer.

Abstract translation: 在半导体器件中，最上层的未掺杂多晶硅层被用作具有高电阻而不进行任何图案化的电阻器。 形成在该电阻器上的金属布线层通过延伸穿过高电阻器件的接触孔连接到形成在电阻器下面的导电层。 此外，通过氧化在电阻器的接触孔中暴露的端部，在高电阻器件和金属布线层之间插入氧化膜以在它们之间实现电绝缘。 以这种方式，通过使用包括未掺杂的多晶硅层的多层多晶硅结构，电阻器由未掺杂的多晶硅层形成。 因此，可以提高积分度，同时放松伴随多层硅结构的阶梯部分，以提高表面的平坦度，并防止上层布线层的差的覆盖层或桥接。

公开(公告)号：US5625215A

公开(公告)日：1997-04-29

申请号：US413014

申请日：1995-03-28

Applicant: Min-Liang Chen ,  Werner Juengling

Inventor： Min-Liang Chen ,  Werner Juengling

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11

CPC classification number: H01L27/1112 ,  Y10S257/904 ,  Y10S257/919

Abstract: SRAM cells are manufactured with balanced, high-resistance load resistances by having substantially all of dielectric layer directly over the polysilicon load resistor covered by a metal layer. The metal layer protects the polysilicon during subsequent processing which can adversely alter its characteristics.

Abstract translation: SRAM单元通过在金属层覆盖的多晶硅负载电阻上直接覆盖基本上所有的介电层，制成平衡的高电阻负载电阻。 金属层在随后的处理期间保护多晶硅，这可以不利地改变其特性。

公开(公告)号：US5622884A

公开(公告)日：1997-04-22

申请号：US655139

申请日：1996-05-30

Applicant: Min-Sea Liu

Inventor： Min-Sea Liu

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904

Abstract: A method is provided for manufacturing a polysilicon load resistor of a semiconductor memory cell. The semiconductor memory cell is formed with at least one transistor and has a semiconductor substrate with a gate dielectric layer on a portion thereof, and a gate electrode layer over the gate dielectric layer. The method includes the steps of: (a) depositing a insulating layer over the gate electrode layer and the remaining portion of the semiconductor substrate around the gate electrode and gate dielectric layers; (b) depositing a polysilicon layer over the insulating layer; (c) implanting ions in the polysilicon layer so as to adjust resistance thereof; (d) etching the polysilicon layer so as to form a high resistance load resistor; (e) etching the insulating layer so as to expose a portion of the gate electrode layer; and (f) forming a metal contact at two ends of the load resistor, one of the metal contacts being located on the exposed portion of the gate electrode so as to establish electrical connection between the gate electrode layer and the load resistor.

Abstract translation: 提供一种制造半导体存储单元的多晶硅负载电阻的方法。 半导体存储单元由至少一个晶体管形成，并且具有在其一部分上具有栅极介电层的半导体衬底，以及栅极电介质层上的栅极电极层。 该方法包括以下步骤：（a）在栅极电极层和围绕栅电极和栅介质层的半导体衬底的剩余部分上沉积绝缘层; （b）在所述绝缘层上沉积多晶硅层; （c）在多晶硅层中注入离子以便调整其电阻; （d）蚀刻多晶硅层以形成高电阻负载电阻; （e）蚀刻所述绝缘层以暴露所述栅电极层的一部分; 和（f）在负载电阻器的两端形成金属接触，其中一个金属触点位于栅电极的露出部分上，以便在栅电极层和负载电阻之间建立电连接。