公开(公告)号：US5254491A

公开(公告)日：1993-10-19

申请号：US763773

申请日：1991-09-23

申请人： Bernard W. Boland ,  Robert B. Davies ,  Paul W. Sanders

发明人： Bernard W. Boland ,  Robert B. Davies ,  Paul W. Sanders

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/763

摘要： A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

公开(公告)号：US5242863A

公开(公告)日：1993-09-07

申请号：US830559

申请日：1991-06-07

申请人： Tu Xiang-Zheng ,  Li Yun-Yan

发明人： Tu Xiang-Zheng ,  Li Yun-Yan

IPC分类号： G01L9/00 ,  H01L21/306 ,  H01L21/762 ,  H01L21/763 ,  H01L21/764

CPC分类号： G01L9/0042 ,  G01L9/0054 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/764 ,  Y10S148/128 ,  Y10S438/96

摘要： A silicon diaphragm piezoresistive pressure sensor having a diaphragm formed by a single-sided fabrication method. The pressure sensor is made up of a substrate on which there is a diaphragm at or near the surface of the substrate with a chamber under the diaphragm. The pressure sensor is fabricated by undercutting a silicon substrate to form a diaphragm and a cavity within the bulk of the substrate under the diaphragm. The fabricating steps including a) forming a buried low resistive layer under a predetermined diaphragm region; b) converting the low resistance layer into porous silicon by anodization of silicon in a concentrated hydrofluoric acid solution; c) removing the porous silicon by selective etching; d) filling the openings formed in the etching of porous silicon with a deposited material to form a sealed reference chamber. Adding appropriate means to the exterior of the diaphragm and substrate to detect changes in pressure between the reference chamber and the surface of the substrate.

摘要翻译： 一种具有通过单面制造方法形成的隔膜的硅隔膜压阻式压力传感器。 压力传感器由基板上形成有隔膜的基板构成，该基板在基板的表面附近或附近具有膜片下方的腔室。 压力传感器通过底切硅衬底以在隔膜的下方的衬底的主体内形成隔膜和空腔来制造。 制造步骤包括：a）在预定的膜片区域下形成掩埋的低电阻层; b）通过在浓缩的氢氟酸溶液中阳极氧化硅将低电阻层转化为多孔硅; c）通过选择性蚀刻去除多孔硅; d）用沉积的材料填充在多孔硅的蚀刻中形成的开口，以形成密封的基准室。 将适当的装置加到隔膜和基板的外部，以检测基准室与基板表面之间的压力变化。

公开(公告)号：US5234861A

公开(公告)日：1993-08-10

申请号：US668013

申请日：1991-03-12

申请人： Roger L. Roisen ,  Curtis H. Rahn ,  John B. Straight ,  Michael S. Liu

发明人： Roger L. Roisen ,  Curtis H. Rahn ,  John B. Straight ,  Michael S. Liu

IPC分类号： H01L21/763

CPC分类号： H01L21/763 ,  Y10S438/902

摘要： An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.

摘要翻译： 隔离结构以及在沉积在衬底上的有源层中使用和制造隔离结构的方法，其制造方法包括以下步骤：在邻近衬底的有源层中形成掩埋氧化物层，在衬底中形成隔离沟槽 通过至少蚀刻到衬底上并且任选地进入衬底，在沟槽的暴露表面上形成介电隔离层，从沟槽的底部去除介电隔离层，并通过外延生长单晶硅形成隔离结构 沟渠。

公开(公告)号：US5223736A

公开(公告)日：1993-06-29

申请号：US704232

申请日：1991-05-22

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L21/763

CPC分类号： H01L21/763

摘要： A structure for and method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30. Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

摘要翻译： 本文公开了一种在半导体本体中形成沟槽的结构和方法。 在要形成沟槽26的n阱8的一部分上生长场氧化物16。 氮化物层20和TEOS氧化物层22沉积。 抗蚀剂24被图案化，TEOS层22，氮化物层20和场氧化物层16被蚀刻。 去除抗蚀剂24，并且通过n阱8蚀刻沟槽26并进入衬底4.然后在沟槽26的侧壁上生长薄氧化物28.多晶硅沉积到沟槽26中并被回蚀以形成多晶硅插塞30.侧壁氧化物32 ，以防止沟槽26的形状中的空隙沿着沟槽26的外边缘形成在多晶硅插塞30的顶部上。为了防止泄漏到沟槽26中，厚的热氧化物盖34生长在沟槽26上。

公开(公告)号：US5217920A

公开(公告)日：1993-06-08

申请号：US900392

申请日：1992-06-18

申请人： Robert J. Mattox ,  Paul R. Proctor ,  Syd R. Wilson

发明人： Robert J. Mattox ,  Paul R. Proctor ,  Syd R. Wilson

IPC分类号： H01L21/306 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76202 ,  H01L21/306 ,  H01L21/743 ,  H01L21/763 ,  Y10S148/05 ,  Y10S148/117

摘要： A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.

摘要翻译： 制造半导体结构的方法包括提供其上形成有至少一层的基板。 至少两个沟槽通过层形成并进入衬底，其中至少一个沟槽用于隔离，并且至少一个沟槽用于与衬底接触。 在沟槽的侧壁上形成沟槽衬垫之后，用掺杂的半导体材料填充沟槽。 然后将用于隔离的沟槽中的掺杂半导体材料进行阳极氧化。 阳极氧化后，阳极氧化的沟槽填充材料被氧化。

公开(公告)号：US5217919A

公开(公告)日：1993-06-08

申请号：US854805

申请日：1992-03-19

申请人： Stephen J. Gaul ,  Donald F. Hemmenway

发明人： Stephen J. Gaul ,  Donald F. Hemmenway

IPC分类号： H01L21/32 ,  H01L21/763

CPC分类号： H01L21/32 ,  H01L21/763

摘要： A process of manufacturing a trench-isolated semiconductor structure comprises forming a first `pad` (e.g. MOS gate) oxide layer on a first surface of a silicon substrate. An oxide etch protective layer of silicon nitride is selectively formed on a first portion of the pad oxide layer so as to overlie a first surface portion of the silicon substrate in which active device regions will be introduced. A second oxide layer is then deposited on the pad oxide layer and on the nitride layer. The dual oxide layer is then patterned to form a trench mask which exposes a second surface portion of the silicon substrate. An etchant is then applied to the structure so as to etch away material from the silicon substrate exposed by the second surface portion and a portion of the second oxide layer, thereby forming a trench in the second surface portion of the silicon substrate. After any remaining portion of the second oxide layer is removed, local oxidation of the structure is performed so as to form a third oxide layer in the trench and a field oxide at surface portions of the substrate adjacent to the nitride layer. A layer of polysilicon is non-selectively deposited over the entire structure to fill the oxide-lined trench and then polished down to the nitride layer which serves as a polishing stop. The nitride is then stripped off the pad oxide in preparation for device region processing.

摘要翻译： 制造沟槽隔离半导体结构的工艺包括在硅衬底的第一表面上形成第一“焊盘”（例如，MOS栅极）氧化层。 在衬垫氧化物层的第一部分上选择性地形成氮化硅的氧化物蚀刻保护层，以覆盖将引入有源器件区域的硅衬底的第一表面部分。 然后在衬垫氧化物层和氮化物层上沉积第二氧化物层。 然后将双重氧化物层图案化以形成暴露硅衬底的第二表面部分的沟槽掩模。 然后将蚀刻剂施加到结构上，以便蚀刻掉由第二表面部分和第二氧化物层的一部分暴露的硅衬底的材料，从而在硅衬底的第二表面部分中形成沟槽。 在除去第二氧化物层的任何剩余部分之后，执行结构的局部氧化，以在沟槽中形成第三氧化物层，并在基板的与氮化物层相邻的表面部分形成场氧化物。 在整个结构上非选择性地沉积多晶硅层以填充氧化物衬里的沟槽，然后抛光到用作抛光停止点的氮化物层。 然后将氮化物从衬垫氧化物上剥离以准备器件区域处理。

公开(公告)号：US5141884A

公开(公告)日：1992-08-25

申请号：US612559

申请日：1990-11-13

申请人： Oh H. Kwon ,  Dong J. Bae

发明人： Oh H. Kwon ,  Dong J. Bae

IPC分类号： H01L29/78 ,  H01L21/316 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L29/66575 ,  H01L21/76227 ,  Y10S438/975

摘要： An isolation method of semiconductor devices comprises the steps of forming a multilayer, defining both active and isolating regions, forming a channel stopper, removing the multilayer on a nitride layer to form a capping oxide layer, removing the multilayer on the nitride layer and a polysilicon layer to form an isolation layer, forming spacers at sidewalls of the isolation region, forming a gate oxide layer and a gate oxide electrode, and forming a second conductive diffusion regions, wherein the CVD process and photolithography methods are applied in formation of the isolating layer not to result in the bird's beak and dislocation caused by stress and the channel stopper is formed by ion-implantation of impurity without its diffusion not to contact with the isolating layer by the spacers on the sidewalls thereof in its diffusion region which is formed by the ion-implantation. Therefore, according to the present invention, the limit of the isolation can be extended into a sub-micron range so as to prevent the narrow channel effect and increase the breakdown voltage.

摘要翻译： 半导体器件的隔离方法包括以下步骤：形成多层，限定有源区和隔离区，形成通道阻挡层，去除氮化物层上的多层以形成覆盖氧化物层，去除氮化物层上的多层和多晶硅 层以形成隔离层，在隔离区的侧壁形成间隔物，形成栅极氧化层和栅极氧化物电极，以及形成第二导电扩散区，其中CVD法和光刻法用于形成隔离层 不会导致鸟的喙和应力引起的位错，并且通过离子注入杂质形成通道阻挡物，而不会使其扩散而不与其隔离层通过其侧壁上的间隔物在其扩散区域中形成，该扩散区由 离子注入。 因此，根据本发明，隔离的极限可以扩展到亚微米范围，以防止窄通道效应并增加击穿电压。

公开(公告)号：US5116779A

公开(公告)日：1992-05-26

申请号：US657770

申请日：1991-02-20

申请人： Katsuji Iguchi

发明人： Katsuji Iguchi

IPC分类号： H01L21/76 ,  H01L21/32 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L21/763 ,  H01L21/32 ,  H01L21/76202

摘要： A process for forming a semiconductor device isolation region which comprises:a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon,b) etching the substrate using a resist pattern to form a trench for providing an isolation region,c) forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall of the trench,d) subsequently forming a first polycrystalline silicon film on the substrate including the trench, leaving the first polycrystalline silicon film only on the side walls of the trench by anisotropic etching and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench, ande) further forming a second polycrystalline silicon film over the semiconductor substrate including the trench, leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching and thereafter oxidizing the remaining second polycrystalline silicon film to thereby form an oxide film.

公开(公告)号：US5017999A

公开(公告)日：1991-05-21

申请号：US374960

申请日：1989-06-30

申请人： Roger L. Roisen ,  Curtis H. Rahn ,  John B. Straight ,  Michael S. Liu

发明人： Roger L. Roisen ,  Curtis H. Rahn ,  John B. Straight ,  Michael S. Liu

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/763

摘要： An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.

公开(公告)号：US5008208A

公开(公告)日：1991-04-16

申请号：US281195

申请日：1988-12-07

申请人： Michael S. Liu ,  Huang-Joung Chen

发明人： Michael S. Liu ,  Huang-Joung Chen

IPC分类号： H01L21/311 ,  H01L21/763

CPC分类号： H01L21/31111 ,  H01L21/763

摘要： A method for making a bipolar integrated circuit structure in a semiconductor substrate. A layer of insulating material having an implantation opening is formed on the upper surface of the semiconductor substrate. A polysilicon layer is formed in the implantation opening. A doping material is implanted into the polysilicon-filled opening. The doping material is diffused into the substrate material from the polysilicon-filled opening.

摘要翻译： 一种在半导体衬底中制造双极集成电路结构的方法。 在半导体衬底的上表面上形成具有注入开口的绝缘材料层。 在植入口中形成多晶硅层。 将掺杂材料注入到多晶硅填充的开口中。 掺杂材料从多晶硅填充的开口扩散到衬底材料中。