公开(公告)号：US5217920A

公开(公告)日：1993-06-08

申请号：US900392

申请日：1992-06-18

申请人： Robert J. Mattox ,  Paul R. Proctor ,  Syd R. Wilson

发明人： Robert J. Mattox ,  Paul R. Proctor ,  Syd R. Wilson

IPC分类号： H01L21/306 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76202 ,  H01L21/306 ,  H01L21/743 ,  H01L21/763 ,  Y10S148/05 ,  Y10S148/117

摘要： A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.

摘要翻译： 制造半导体结构的方法包括提供其上形成有至少一层的基板。 至少两个沟槽通过层形成并进入衬底，其中至少一个沟槽用于隔离，并且至少一个沟槽用于与衬底接触。 在沟槽的侧壁上形成沟槽衬垫之后，用掺杂的半导体材料填充沟槽。 然后将用于隔离的沟槽中的掺杂半导体材料进行阳极氧化。 阳极氧化后，阳极氧化的沟槽填充材料被氧化。

公开(公告)号：US4943539A

公开(公告)日：1990-07-24

申请号：US350665

申请日：1989-05-09

申请人： Syd R. Wilson ,  James A. Sellers ,  Robert J. Mattox

发明人： Syd R. Wilson ,  James A. Sellers ,  Robert J. Mattox

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76814 ,  H01L21/7688 ,  Y10S438/97

摘要： A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer is formed over a bottom interconnect layer, and an interlayer dielectric is formed on the sacrificial layer. A via is etched in the interlayer dielectric, exposing the sacrificial layer. The sacrificial layer is isotropically etched to expose an area of the interconnect metal that is larger than the area of the via and a via metallization is selectively formed on the interconnect metal by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer, is filled with the via metallization, thereby providing a contact area to the bottom interconnect metal which is larger than the via metallization itself.

公开(公告)号：US4801350A

公开(公告)日：1989-01-31

申请号：US947069

申请日：1986-12-29

申请人： Robert J. Mattox ,  Frederick J. Robinson

发明人： Robert J. Mattox ,  Frederick J. Robinson

IPC分类号： H01L21/033 ,  B44C1/22 ,  C03C15/00 ,  H01L21/306

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  Y10S438/947

摘要： A method for the construction of submicron features using optical lithography technology. A material is deposited on a surface to be etched, this material is partially etched through using optical lithography technology. Sidewalls are deposited to reduce the size of this etched area to the submicron size desired. The etch of the layer is then completed resulting in a submicron mask for the substrate below.

摘要翻译： 使用光刻技术构建亚微米特征的方法。 材料沉积在要蚀刻的表面上，该材料通过使用光刻技术被部分蚀刻。 沉积侧壁以将该蚀刻区域的尺寸减小到所需的亚微米尺寸。 然后完成该层的蚀刻，得到下面的基底的亚微米掩模。

公开(公告)号：US4791073A

公开(公告)日：1988-12-13

申请号：US122094

申请日：1987-11-17

申请人： Andrew G. Nagy ,  Robert J. Mattox

发明人： Andrew G. Nagy ,  Robert J. Mattox

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/471 ,  H01L21/475

CPC分类号： H01L21/02063 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76224

摘要： A method is described for forming dielectric filled isolation trenches in semiconductor substrates in which a differentially etchable etch-stop layer is provided above the surface of the substrate during the trench filling process so that the height of the trench filling relative to the surface of the substrate may be adjusted for optimum overall results during subsequent fabrication steps and so that the substrate surface may be protected from contact with the etching reagents used during planarization of the trench filling material. This avoids damage to the substrate surface and permits improved surface planarity.