公开(公告)号：US09035349B2

公开(公告)日：2015-05-19

申请号：US13768730

申请日：2013-02-15

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Nicolas Guitard ,  Thomas Benoist

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/87

CPC classification number: H01L29/7424 ,  H01L27/0262 ,  H01L29/87

Abstract: A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.

Abstract translation: 一种器件包括在绝缘体上的硅层内的包括具有第一类型导电性的中心区域的中心半导体区域，具有与第一类型导电性相反的第二类型导电率的第二类型的中间区域分别设置在 并且与中心区域接触以形成两个PN结，两个半导体端部区域分别设置在中心区域的任一侧上，每个端部区域包括与相邻中间区域接触的相反导电类型的两个端部区域， 每个端部区域的两个端部区域相互电连接以形成装置的两个端子。

公开(公告)号：US09013228B2

公开(公告)日：2015-04-21

申请号：US14160369

申请日：2014-01-21

Applicant: STMicroelectronics SA

Inventor： Frédéric Hasbani

IPC: G05F1/10 ,  H03K19/00

CPC classification number: H03K19/0016 ,  H03K19/0013 ,  H03K2217/0018

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract translation: 本公开中描述的实施例涉及一种用于为集成系统提供电力的方法，包括以下动作：向系统提供电源，接地和体偏置电压，体偏置电压包括p沟道MOS晶体管的体偏置电压， 大于或低于电源电压，以及n沟道MOS晶体管的体偏置电压低于或大于接地电压，根据系统的处理单元是否由系统提供的电压进行选择 在活动或不活动的时段期间，提供用于偏置处理单元的MOS晶体管的主体的电压，以及为处理单元的MOS晶体管的主体提供所选择的电压。

公开(公告)号：US09012955B2

公开(公告)日：2015-04-21

申请号：US13921436

申请日：2013-06-19

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: H01L29/749 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L29/749 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/1203 ,  H01L27/1207

Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

Abstract translation: 保护在被布置在绝缘层本身上的SOI型半导体层中形成的过电压的MOS晶体管，其本身布置在半导体衬底上，该半导体衬底包括至少部分地在MOS晶体管下方形成在衬底中的横向场效应控制晶闸管，场效应转 所述晶闸管的区域在所述MOS晶体管的主电极的至少一部分的下方延伸并且被所述绝缘层分离，所述晶闸管的阳极和阴极分别连接到所述MOS的漏极和源极 晶体管，由此在MOS晶体管的漏极和源极之间的正过电压的情况下晶闸管导通。

公开(公告)号：US20150093067A1

公开(公告)日：2015-04-02

申请号：US14492435

申请日：2014-09-22

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER ,  Frédéric BOEUF

IPC: G02F1/225

CPC classification number: G02F1/025 ,  G02F1/225 ,  G02F2001/212

Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.

Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。

公开(公告)号：US20150086154A1

公开(公告)日：2015-03-26

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/122 ,  H01L27/02 ,  H01L25/16

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。

公开(公告)号：US20150054042A1

公开(公告)日：2015-02-26

申请号：US14462724

申请日：2014-08-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Sebastien Jouan ,  Laurent Frey ,  Salim Boutami

IPC: H01L27/144 ,  H01L31/101 ,  H01L29/49 ,  H01L29/66 ,  H01L29/16 ,  H01L31/18 ,  H01L31/107

CPC classification number: H01L27/1443 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/6656 ,  H01L31/02327 ,  H01L31/1016 ,  H01L31/107 ,  H01L31/1804

Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.

Abstract translation: 光电二极管包括布置在光电二极管半导体衬底的光接收表面上的至少一个中心衬垫。 衬垫由第一材料制成，并且包括由具有与第一材料不同的光学折射率的第二材料制成的间隔件包围的侧壁。 焊盘的横向尺寸小于光电二极管的工作波长。 第一和第二材料都对该工作波长是透明的。 焊盘和间隔物同时形成栅电极和MOS晶体管的侧壁间隔物。

公开(公告)号：US20150044841A1

公开(公告)日：2015-02-12

申请号：US14450385

申请日：2014-08-04

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Perrine BATUDE ,  Jean-Michel HARTMANN ,  Benoit SKLENARD ,  Maud VINET

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/16 ,  H01L29/417

CPC classification number: H01L29/66568 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28088 ,  H01L29/16 ,  H01L29/161 ,  H01L29/41766 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.

Abstract translation: 晶体管的制造方法，包括以下步骤：在晶体管沟道区的任一侧的半导体层中形成牺牲区，在所述牺牲区上形成抵靠所述晶体管的栅极的侧面的绝缘间隔物，去除所述牺牲区 以便形成空腔，其中所述空腔在所述通道区域的任一侧上延伸并且穿过所述间隔件，在所述空腔中形成掺杂的半导体材料，所述半导体材料穿透在所述间隔件下方。

公开(公告)号：US20150043828A1

公开(公告)日：2015-02-12

申请号：US14452761

申请日：2014-08-06

Applicant: STMicroelectronics SA

Inventor： Stéphane Valente

IPC: G06K9/62 ,  G06K9/46

CPC classification number: G06K9/6202 ,  G06K9/46 ,  G06K9/4671 ,  G06K2009/4666 ,  G06K2009/6213

Abstract: A method for extracting characteristic points from an image, includes extracting characteristic points from a first image, generating for each characteristic point a descriptor with several components describing an image region around the characteristic point, and comparing two by two the descriptors of the first image, the characteristic points whose descriptors have a proximity between them greater than an ambiguity threshold, being considered ambiguous.

Abstract translation: 一种用于从图像中提取特征点的方法，包括从第一图像中提取特征点，为每个特征点生成描述符包含描述特征点周围的图像区域的描述符的描述符，并且将第二图像的描述符比较两个， 其描述符之间的接近度大于歧义阈值的特征点被认为是不明确的。

公开(公告)号：US20140361914A1

公开(公告)日：2014-12-11

申请号：US14293119

申请日：2014-06-02

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.,

Inventor： Pratap Narayan SINGH ,  Stéphane LE TUAL

IPC: H03K17/22 ,  H03M1/12

CPC classification number: H03K17/223 ,  H03K17/145 ,  H03K17/687 ,  H03K2217/0018 ,  H03M1/12

Abstract: The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.

Abstract translation: 本发明涉及一种电路，包括：具有第一和第二主电流节点的第一晶体管（102）和适于接收用于使第一晶体管在导通状态与非导通状态之间转变的第一定时信号（CLK）的栅极节点; 偏置电路（108），耦合到所述第一晶体管的另一节点; 以及适于控制所述偏置电路以对所述另一节点施加第一控制电压（VCTRL）以调整至少一个所述转换的定时的控制电路（110）。

公开(公告)号：US20140361440A1

公开(公告)日：2014-12-11

申请号：US14287343

申请日：2014-05-27

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： PIERRE BAR ,  Simon GOUSSEAU ,  Yann BEILLIARD

IPC: H01L23/373 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/4275 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/73204

Abstract: A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure.

Abstract translation: 用于在衬底内部生产至少一个穿硅的方法可包括在衬底的第一侧从衬底的第一侧形成空腔，直到导电部分出现。 该方法还可以包括在空腔的底部和壁上形成导电层，并且至少部分地在空腔外部的第一侧上形成导电层。 该方法还可以包括用至少一种相变材料至少部分地填充空腔。 另一方面涉及三维综合结构。