公开(公告)号：US20100001349A1

公开(公告)日：2010-01-07

申请号：US12495501

申请日：2009-06-30

Applicant: Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

Inventor： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC: H01L27/088

CPC classification number: H01L21/823425 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/66825

Abstract: A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

Abstract translation: 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US07642589B2

公开(公告)日：2010-01-05

申请号：US11433942

申请日：2006-05-15

Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

Abstract: A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

Abstract translation: 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。

公开(公告)号：US07535061B2

公开(公告)日：2009-05-19

申请号：US11586225

申请日：2006-10-25

Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

IPC: H01L21/84

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

Abstract translation: 提供了场效应晶体管（Fin-FET）。 翅片设置在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层设置在沟槽中，使得第一绝缘层的表面在鳍片的暴露翅片侧壁的表面下方凹进。 保护层设置在第一绝缘层上，第二绝缘层设置在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。

公开(公告)号：US07534686B2

公开(公告)日：2009-05-19

申请号：US11589718

申请日：2006-10-31

Applicant: Deok Hyung Lee ,  Byeong Chan Lee ,  In Soo Jung ,  Yong Hoon Son ,  Siyoung Choi ,  Taek Jung Kim

Inventor： Deok Hyung Lee ,  Byeong Chan Lee ,  In Soo Jung ,  Yong Hoon Son ,  Siyoung Choi ,  Taek Jung Kim

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.

Abstract translation: 公开了一种可用于FinFET器件的半导体鳍片结构，其结合了上部区域和下部区域，其中上部区域形成有基本上垂直的侧壁，并且下部区域形成有倾斜的侧壁以产生更宽的基部。 所公开的半导体鳍片结构通常还将包括在上部区域和下部区域之间的界面处的水平台阶区域。 还公开了一系列制造具有这种双重结构的半导体鳍片的半导体器件的方法，并结合了诸如二氧化硅和/或氮化硅的绝缘材料的各种组合，用于在相邻的半导体鳍片之间形成浅沟槽隔离（STI）结构。

公开(公告)号：US07521301B2

公开(公告)日：2009-04-21

申请号：US11530651

申请日：2006-09-11

Applicant: Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66803

Abstract: Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described.

Abstract translation: 集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。 沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。 源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。 还描述了相关的制造方法。

公开(公告)号：US07511340B2

公开(公告)日：2009-03-31

申请号：US11779477

申请日：2007-07-18

Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Chul-Sung Kim ,  In-Soo Jung ,  Jong-Ryeol Yoo

Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Chul-Sung Kim ,  In-Soo Jung ,  Jong-Ryeol Yoo

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/10888 ,  H01L21/28525 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S257/90 ,  H01L2924/00

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract translation: 半导体器件在半导体衬底上具有栅极结构，在相应栅极结构的侧壁上具有第一间隔物。 第一接触垫位于栅极结构之间并且具有低于栅极结构的高度的高度。 第二间隔件设置在第一间隔件的侧壁和第一接触垫的暴露的侧壁上。 第二接触垫设置在第一接触垫上。

公开(公告)号：US20080308845A1

公开(公告)日：2008-12-18

申请号：US12195790

申请日：2008-08-21

Applicant: Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

Inventor： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

IPC: H01L29/00

CPC classification number: H01L29/0653 ,  H01L29/78

Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

Abstract translation: 本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路。 根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件 半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。 在本发明的实施例中可以去除第二组IV图案。 在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

公开(公告)号：US20080093601A1

公开(公告)日：2008-04-24

申请号：US11974293

申请日：2007-10-12

Applicant: Pil-Kyu Kang ,  Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Byeong-Chan Lee ,  In-Soo Jung

Inventor： Pil-Kyu Kang ,  Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Byeong-Chan Lee ,  In-Soo Jung

IPC: H01L29/786 ,  H01L29/12 ,  H01L21/84

CPC classification number: H01L21/823425 ,  H01L21/823475

Abstract: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.

Abstract translation: 在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。 绝缘层图案在其中具有部分地暴露第一单晶层的开口。 种子层在开口处。 第二单晶层位于绝缘层图案和籽晶层上。 第二单晶层具有与种子层基本相同的晶体结构。 转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。 转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

公开(公告)号：US07320908B2

公开(公告)日：2008-01-22

申请号：US11072103

申请日：2005-03-04

Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Jong-Wook Lee ,  In-Soo Jung ,  Deok-Hyung Lee

Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Jong-Wook Lee ,  In-Soo Jung ,  Deok-Hyung Lee

IPC: H01L21/338

CPC classification number: H01L29/7851 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66621

Abstract: Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.

Abstract translation: 提供了形成半导体器件的方法。 蚀刻半导体衬底，使得半导体衬底限定沟槽和初步活性图案。 沟槽具有地板和侧壁。 绝缘层设置在地板上，并且沟槽的侧壁和间隔件形成在绝缘层上，使得间隔件位于沟槽的侧壁和沟槽底部的一部分上。 绝缘层在沟槽的地板上移除并且在间隔物的下面被移除，使得沟槽的底部的一部分至少部分地露出，间隔物与沟槽的底部间隔开，并且预活性图案的一部分 部分暴露。 部分地去除预活性图案的暴露部分的一部分以提供在间隔物下方限定凹陷部分的活性图案。 在活性图案的凹部中形成掩埋绝缘层。 还提供了相关设备。

公开(公告)号：US07122871B2

公开(公告)日：2006-10-17

申请号：US10801614

申请日：2004-03-16

Applicant: Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66803

Abstract: Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described.

Abstract translation: 集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。 沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。 源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。 还描述了相关的制造方法。