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    Method of forming insulating layer and method of manufacturing transistor using the same
    1.
    发明授权
    Method of forming insulating layer and method of manufacturing transistor using the same 有权
    形成绝缘层的方法和使用其制造晶体管的方法

    公开(公告)号：US08183136B2

    公开(公告)日：2012-05-22

    申请号：US12950592

    申请日：2010-11-19

    申请人： Seong-Hoon Jeong ,  Dong-Chan Kim ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Deok-Hyung Lee

    发明人： Seong-Hoon Jeong ,  Dong-Chan Kim ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Deok-Hyung Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L21/3144 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28238 ,  H01L29/51

    摘要： Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.

    摘要翻译： 提供一种形成绝缘层的方法和使用该方法制造晶体管的方法。 形成绝缘层的方法包括在含硅（Si）的衬底上形成包括氧化硅（SiO 2）的预备绝缘层。 含有氨（NH 3）气体的反应性气体被供给到初级绝缘层。 使用等离子体从氨气产生氮自由基（N *）和氢自由基（H *）。 氢原子与初级绝缘层的氧结合，氮自由基与氧化硅结合，从而可以形成包含氢氧化物（OH）和氧氮化硅（SiON）的绝缘层。

    NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same
    3.
    发明授权
    NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same 有权
    包括具有抗穿透杂质区域的选择晶体管的NAND型闪存器件及其制造方法

    公开(公告)号：US07683421B2

    公开(公告)日：2010-03-23

    申请号：US11849533

    申请日：2007-09-04

    申请人： Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    发明人： Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    IPC分类号： H01L29/10

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/12 ,  H01L29/1083 ,  H01L29/78

    摘要： A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.

    摘要翻译： 提供了包括选择晶体管的NAND型闪速存储器件。 该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。 第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。 多个单元栅极图案设置在第一和第二选择栅极图案之间。 在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。 第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。 在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。 第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

    Fin field effect transistors including epitaxial fins
    5.
    发明授权
    Fin field effect transistors including epitaxial fins 有权
    Fin场效应晶体管包括外延鳍片

    公开(公告)号：US07394117B2

    公开(公告)日：2008-07-01

    申请号：US11622103

    申请日：2007-01-11

    申请人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    发明人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC分类号： H01L29/34

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比有源区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。

    Finfets having first and second gates of different resistivities
    9.
    发明授权
    Finfets having first and second gates of different resistivities 有权
    Finfets具有不同电阻率的第一和第二门

    公开(公告)号：US07268396B2

    公开(公告)日：2007-09-11

    申请号：US10937246

    申请日：2004-09-09

    申请人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

    IPC分类号： H01L29/772

    CPC分类号： H01L29/785 ,  H01L21/823842 ,  H01L29/42384 ,  H01L29/66795

    摘要： A fin field effect transistor (FinFET) includes a first gate and a second gate. The first gate has a vertical part that is defined by sidewalls of a silicon fin and sidewalls of a capping pattern disposed on the silicon fin and a horizontal part horizontally extends from the vertical part. The second gate is made of a low-resistivity material and is in direct contact with the horizontal part of the first gate. A channel may be controlled due to the first gate, and a device operating speed may be enhanced due to the second gate. Related fabrication methods also are described.

    摘要翻译： 鳍状场效应晶体管（FinFET）包括第一栅极和第二栅极。 第一栅极具有由硅翅片的侧壁和设置在硅片上的封盖图案的侧壁限定的垂直部分，并且水平部分从垂直部分水平延伸。 第二栅极由低电阻率材料制成，并与第一栅极的水平部分直接接触。 由于第一门可以控制通道，并且由于第二门可能会增强设备运行速度。 还描述了相关的制造方法。

    FIN FIELD EFFECT TRANSISTORS INCLUDING EPITAXIAL FINS
    10.
    发明申请
    FIN FIELD EFFECT TRANSISTORS INCLUDING EPITAXIAL FINS 有权
    包括外源性FINS的FIN场效应晶体管

    公开(公告)号：US20070111439A1

    公开(公告)日：2007-05-17

    申请号：US11622103

    申请日：2007-01-11

    申请人： In Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    发明人： In Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC分类号： H01L21/8242 ,  H01L29/76

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比活性区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。