公开(公告)号：US20100155846A1

公开(公告)日：2010-06-24

申请号：US12317126

申请日：2008-12-19

Applicant: Niloy Mukherjee ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack Kavalieros ,  Robert S. Chau

Inventor： Niloy Mukherjee ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack Kavalieros ,  Robert S. Chau

IPC: H01L29/78 ,  H01L21/04

CPC classification number: H01L29/517 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/452 ,  H01L29/456 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract translation: 与源极或漏极区的接触。 接触件具有导电材料，但是导电材料通过绝缘体与源极或漏极区域分离。

公开(公告)号：US07736956B2

公开(公告)日：2010-06-15

申请号：US12079587

申请日：2008-03-26

Applicant: Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Gilbert Dewey ,  Mark L. Doczy ,  Robert S. Chau

Inventor： Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Gilbert Dewey ,  Mark L. Doczy ,  Robert S. Chau

IPC: H01L29/72

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/42384 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

Abstract translation: 本发明的实施例提供一种具有金属栅极，高k栅极电介质层，金属栅极下方距离的源极/漏极延伸部以及金属栅极侧面中的横向底切的器件。

公开(公告)号：US20100059821A1

公开(公告)日：2010-03-11

申请号：US12590562

申请日：2009-11-10

Applicant: Rafael Rios ,  Jack Kavalieros ,  Stephen M. Cea

Inventor： Rafael Rios ,  Jack Kavalieros ,  Stephen M. Cea

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

Abstract translation: 形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。 翅片的氧化部分隔离被氮化物盖保护的半导体主体。 然后可以去除氮化物盖。 热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

公开(公告)号：US20090315101A1

公开(公告)日：2009-12-24

申请号：US12145020

申请日：2008-06-24

Applicant: Willy Rachmady ,  Jack Kavalieros

Inventor： Willy Rachmady ,  Jack Kavalieros

IPC: H01L29/78 ,  H01L21/764

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.

Abstract translation: 形成用于非平面晶体管的缺口基隔离物轮廓的方法包括提供在衬底上具有通道区域的半导体鳍片，并且形成与沟道区域的侧壁相邻并且在沟道区域的顶表面上的栅电极， 栅电极在顶表面上具有硬掩模。 使用增强的化学气相沉积（PE-CVD）工艺在栅极和散热片上沉积间隔层。 将多蚀刻工艺应用于间隔层，以在栅电极的横向相对侧上形成一对凹口，其中每个凹口位于翅片的侧壁和鳍的顶表面附近。

公开(公告)号：US20090280608A9

公开(公告)日：2009-11-12

申请号：US11556025

申请日：2006-11-02

Applicant: Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

Inventor： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

IPC: H01L21/77 ,  H01L21/762 ,  H01L21/04

CPC classification number: H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract translation: 对半导体装置及其形成方法进行说明。 半导体器件包括形成在衬底的第一部分上的金属NMOS栅极电极和形成在衬底的第二部分上的硅化物PMOS栅极电极。

公开(公告)号：US20090261391A1

公开(公告)日：2009-10-22

申请号：US12493291

申请日：2009-06-29

Applicant: Jack KAVALIEROS ,  Annalisa CAPPELLANI ,  Justin K. BRASK ,  Mark L. DOCZY ,  Matthew V. METZ ,  Suman DATTA ,  Chris E. BARNS ,  Robert S. CHAU

Inventor： Jack KAVALIEROS ,  Annalisa CAPPELLANI ,  Justin K. BRASK ,  Mark L. DOCZY ,  Matthew V. METZ ,  Suman DATTA ,  Chris E. BARNS ,  Robert S. CHAU

IPC: H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7834

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.

Abstract translation: 互补金属氧化物半导体集成电路可以形成有使用替换金属栅极和升高源极漏极形成的PMOS器件。 凸起的源极漏极可以由掺杂p型的外延沉积的硅锗材料形成。 替代金属栅极工艺导致金属栅电极，并且可能涉及去除氮化物蚀刻停止层。

公开(公告)号：US07575991B2

公开(公告)日：2009-08-18

申请号：US10882733

申请日：2004-06-30

Applicant: Mark L. Doczy ,  Robert L. Norman ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Robert L. Norman ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert S. Chau

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28176 ,  H01L21/3105 ,  H01L21/31111 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517

Abstract: A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid.

Abstract translation: 基板上的金属氧化物层至少部分地转变为金属层。 金属层的至少一部分被抗氧化盖覆盖。 被覆层和下面的金属可以被除去，例如使用酸。

公开(公告)号：US20090179282A1

公开(公告)日：2009-07-16

申请号：US12353766

申请日：2009-01-14

Applicant: Brian S. Doyle ,  Jack Kavalieros ,  Justin K. Brask ,  Matthew V. Mertz ,  Mark L. Doczy ,  Suman Datta ,  Robert S. Chau

Inventor： Brian S. Doyle ,  Jack Kavalieros ,  Justin K. Brask ,  Matthew V. Mertz ,  Mark L. Doczy ,  Suman Datta ,  Robert S. Chau

IPC: H01L29/78

CPC classification number: H01L21/26513 ,  H01L21/2652 ,  H01L21/28247 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66628

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.

Abstract translation: 本发明的实施例提供一种具有金属栅极，高k栅极电介质层和在高k栅极电介质层下面的衬底的氧化减少的器件。 在高k栅极电介质层和金属栅极上的氧阻挡层或覆盖层可以在诸如离子注入区域的间隔物形成和退火的过程期间防止这种氧化。

公开(公告)号：US20090168498A1

公开(公告)日：2009-07-02

申请号：US12006063

申请日：2007-12-28

Applicant: Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

Inventor： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

IPC: G11C11/40 ,  H01L21/283

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.

Abstract translation: 通常，一方面，一种方法包括形成具有N-扩散和P-扩散区域的半导体衬底。 在半导体衬底上形成栅叠层。 栅电极硬掩模形成在栅叠层上。 栅极电极硬掩模用隔离材料增加在通过栅极晶体管周围。 使用增强的栅极电极硬掩模蚀刻栅极堆叠以形成栅电极。 通过栅极周围的栅电极具有比其它栅电极更大的长度。

公开(公告)号：US20090166769A1

公开(公告)日：2009-07-02

申请号：US11968099

申请日：2007-12-31

Applicant: Matthew V. Metz ,  Mark L. Doczy ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Matthew V. Metz ,  Mark L. Doczy ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L21/324 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/785

Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.

Abstract translation: 描述形成微电子结构的方法。 那些方法可以包括在衬底上形成栅极电介质层，在栅极电介质层上形成金属栅极层，然后在原位在金属栅极层上形成多晶硅层，其中金属栅极层不暴露于空气中。