公开(公告)号：US09048314B2

公开(公告)日：2015-06-02

申请号：US14465636

申请日：2014-08-21

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/267 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US09006707B2

公开(公告)日：2015-04-14

申请号：US11712191

申请日：2007-02-28

Applicant: Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

Inventor： Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/8252 ,  B82Y10/00 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/04

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/151 ,  H01L29/201 ,  H01L29/207 ,  H01L29/365

Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于形成逻辑器件的方法，包括在硅（Si）衬底上形成n型半导体器件，该衬底包括基于砷化铟镓（InGaAs）的堆叠，其包括第一缓冲层， 形成在第一缓冲层上的第二缓冲层，形成在第二缓冲层上的第一器件层。 此外，该方法可以包括从基于InGaAs的叠层在Si衬底上形成p型半导体器件，并且在n型半导体器件和p型半导体器件之间形成隔离。 描述和要求保护其他实施例。

公开(公告)号：US20130146945A1

公开(公告)日：2013-06-13

申请号：US13752272

申请日：2013-01-28

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/267

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US08405164B2

公开(公告)日：2013-03-26

申请号：US12767681

申请日：2010-04-26

Applicant: Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

Inventor： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC: H01L29/06

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

Abstract translation: 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

公开(公告)号：US08294180B2

公开(公告)日：2012-10-23

申请号：US13038190

申请日：2011-03-01

Applicant: Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

Inventor： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L29/66

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

Abstract translation: 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20120205729A1

公开(公告)日：2012-08-16

申请号：US13453403

申请日：2012-04-23

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/772

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract translation: 描述具有窄带隙半导体源极/漏极区域的晶体管。 晶体管包括形成在形成于硅层上的栅介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

公开(公告)号：US08232588B2

公开(公告)日：2012-07-31

申请号：US12749389

申请日：2010-03-29

Applicant: Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

Inventor： Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852

Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.

Abstract translation: 描述了增加存储单元电容器的表面积的方法和装置。 形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。 衬底具有翅片。 第一绝缘层沉积在邻近鳍片的衬底上。 第二绝缘层上的开口形成在鳍上。 第一导电层沉积在第二绝缘层和鳍上。 第三绝缘层沉积在第一导电层上。 在第三绝缘层上沉积第二导电层。 第二导电层填充开口。 第二导电层是提供与上金属层的互连。 从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

公开(公告)号：US08148786B2

公开(公告)日：2012-04-03

申请号：US12493291

申请日：2009-06-29

Applicant: Jack Kavalieros ,  Annalisa Cappellani ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Chris E. Barns ,  Robert S. Chau

Inventor： Jack Kavalieros ,  Annalisa Cappellani ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Chris E. Barns ,  Robert S. Chau

IPC: H01L21/76

CPC classification number: H01L29/66636 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7834

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.

Abstract translation: 互补金属氧化物半导体集成电路可以形成有使用替换金属栅极和升高源极漏极形成的PMOS器件。 凸起的源极漏极可以由掺杂p型的外延沉积的硅锗材料形成。 替代金属栅极工艺导致金属栅电极，并且可能涉及去除氮化物蚀刻停止层。

公开(公告)号：US20120061649A1

公开(公告)日：2012-03-15

申请号：US13160886

申请日：2011-06-15

Applicant: Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

Inventor： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L29/1033 ,  H01L29/0673 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract translation: 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

公开(公告)号：US08071983B2

公开(公告)日：2011-12-06

申请号：US12463309

申请日：2009-05-08

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

IPC: H01L29/10

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract translation: 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。