公开(公告)号：US07772021B2

公开(公告)日：2010-08-10

申请号：US11947725

申请日：2007-11-29

Applicant: Je-hun Lee ,  Dong-ju Yang ,  Tae-hyung Ihn ,  Do-hyun Kim ,  Sun-young Hong ,  Seung-jae Jung ,  Chang-oh Jeong ,  Eun-guk Lee

Inventor： Je-hun Lee ,  Dong-ju Yang ,  Tae-hyung Ihn ,  Do-hyun Kim ,  Sun-young Hong ,  Seung-jae Jung ,  Chang-oh Jeong ,  Eun-guk Lee

IPC: H01L21/00 ,  G02F1/136 ,  H01L29/16 ,  H01L31/00

CPC classification number: H01L29/7869

Abstract: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

Abstract translation: 提供一种制造半导体氧化物薄膜晶体管（TFT）衬底的方法。 该方法包括在绝缘基板上形成栅极布线; 并且形成其中半导体氧化物膜图案和数据布线堆叠在栅极布线上的结构，其中半导体氧化物膜图案被选择性地图案化以具有第二厚度的第一厚度的沟道区域和源极/漏极区域，并且其中图像数据 通过形成在源极区域上的数据布线耦合到源极区域。 根据4掩模实施例，数据布线和半导体氧化膜图案由共享蚀刻掩模限定。

公开(公告)号：US07767478B2

公开(公告)日：2010-08-03

申请号：US12031121

申请日：2008-02-14

Applicant: Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

Inventor： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC: H01L21/00

CPC classification number: H01L27/3279 ,  H01L27/124 ,  H01L27/1288 ,  H01L51/0023 ,  H01L51/56

Abstract: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

Abstract translation: 本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

公开(公告)号：US20100123136A1

公开(公告)日：2010-05-20

申请号：US12333831

申请日：2008-12-12

Applicant: Je-Hun LEE ,  Do-Hyun Kim ,  Tae-Hyung Ihn

Inventor： Je-Hun LEE ,  Do-Hyun Kim ,  Tae-Hyung Ihn

IPC: H01L23/48 ,  H01L21/3205 ,  H01L33/00

CPC classification number: H01L29/7869

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract translation: 在衬底上形成氧化物或氮化物半导体层。 包括第一元件和第二元件的第一导电层和包括第二元件的第二导电层形成在半导体层上。 第一元件通过热处理或激光照射在第一导电层和氧化物或氮化物半导体层之间的界面区域附近被氧化或氮化。 第一元素的氧化物形成的吉布斯自由能低于第二元素或氧化物或氮化物半导体层中的任何元素的自由能。

公开(公告)号：US20100022041A1

公开(公告)日：2010-01-28

申请号：US12576217

申请日：2009-10-08

Applicant: Je-Hun LEE ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

Inventor： Je-Hun LEE ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC: H01L21/16

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract translation: 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US20090162982A1

公开(公告)日：2009-06-25

申请号：US12392629

申请日：2009-02-25

Applicant: Je-Hun Lee ,  Do-Hyun Kim ,  Eun-Guk Lee ,  Chang-Oh Jeong

Inventor： Je-Hun Lee ,  Do-Hyun Kim ,  Eun-Guk Lee ,  Chang-Oh Jeong

IPC: H01L21/336

CPC classification number: G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/124

Abstract: An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

Abstract translation: 阵列基板包括开关元件，信号传输线，钝化层和像素电极。 开关元件设置在绝缘基板上。 信号传输线连接到开关元件，并且包括阻挡层，导电线和氮化铜层。 阻挡层设置在绝缘基板上。 导电线设置在阻挡层上并且包括铜或铜合金。 氮化铜层覆盖导电线。 钝化层覆盖开关元件和信号传输线，并且具有接触孔，开关元件的漏电极通过该接触孔部分露出。 像素电极设置在绝缘基板上，并通过接触孔与开关元件的漏电极连接。

公开(公告)号：US07511302B2

公开(公告)日：2009-03-31

申请号：US11049742

申请日：2005-02-04

Applicant: Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

Inventor： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

IPC: H01L27/14

CPC classification number: H01L29/66765 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

Abstract: Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

Abstract translation: 在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。 铝层沉积在钼层上。 可以在铝层上形成另一金属层。 钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

公开(公告)号：US20080318368A1

公开(公告)日：2008-12-25

申请号：US12153674

申请日：2008-05-22

Applicant: Myung-kwan Ryu ,  Sang-yoon Lee ,  Je-hun Lee ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

Inventor： Myung-kwan Ryu ,  Sang-yoon Lee ,  Je-hun Lee ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

IPC: H01L21/00

CPC classification number: H01L29/7869

Abstract: Provided is a method of manufacturing a ZnO-based thin film transistor (TFT). The method may include forming source and drain electrodes using one or two wet etchings. A tin (Sn) oxide, a fluoride, or a chloride having relatively stable bonding energy against plasma may be included in a channel layer. Because the source and drain electrodes are formed by wet etching, damage to the channel layer and an oxygen vacancy may be prevented or reduced. Because the material having higher bonding energy is distributed in the channel layer, damage to the channel layer occurring when a passivation layer is formed may be prevented or reduced.

Abstract translation: 提供了一种制造ZnO基薄膜晶体管（TFT）的方法。 该方法可以包括使用一个或两个湿蚀刻来形成源极和漏极。 对于等离子体具有相对稳定的结合能的锡（Sn）氧化物，氟化物或氯化物可以包括在通道层中。 因为源电极和漏电极是通过湿蚀刻形成的，所以可以防止或减少对沟道层的损伤和氧空位。 因为具有较高结合能的材料分布在沟道层中，所以可以防止或减少在形成钝化层时对沟道层的损坏。

公开(公告)号：US20080308826A1

公开(公告)日：2008-12-18

申请号：US11930502

申请日：2007-10-31

Applicant: Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

Inventor： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

Abstract translation: 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。

公开(公告)号：US20080185590A1

公开(公告)日：2008-08-07

申请号：US11930536

申请日：2007-10-31

Applicant: Byoung-June Kim ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

Inventor： Byoung-June Kim ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

IPC: H01L29/04 ,  H01L21/84

CPC classification number: H01L27/1255 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract translation: 薄膜晶体管（TFT）的制造方法包括形成包括可以与硅组合的金属的栅电极，以在衬底上形成硅化物，并通过在栅极电极中向栅电极提供包括硅的气体形成栅极绝缘层 该方法还包括在栅极绝缘层上形成半导体，在半导体上形成数据线和漏极并形成连接到漏电极的像素电极。

公开(公告)号：US20080123039A1

公开(公告)日：2008-05-29

申请号：US11938023

申请日：2007-11-09

Applicant: Eun-guk Lee ,  Je-hun Lee ,  Do-hyun Kim ,  Chang-oh Jeong

Inventor： Eun-guk Lee ,  Je-hun Lee ,  Do-hyun Kim ,  Chang-oh Jeong

IPC: G02F1/1345 ,  G02F1/1333

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F2001/133357

Abstract: In a liquid crystal display, an adhesion layer is provided between an insulating substrate and a wiring feature having very low resistance (e.g. a copper gate line). The adhesion layer may have a thickness of 190 to 210 nm. Good adhesion and high light transmittance can be obtained.

Abstract translation: 在液晶显示器中，在绝缘基板和具有非常低电阻的布线特征（例如铜栅极线）之间设置粘附层。 粘合层的厚度可以为190〜210nm。 可以获得良好的附着力和高的透光率。