公开(公告)号：US20120154008A1

公开(公告)日：2012-06-21

申请号：US13162702

申请日：2011-06-17

Applicant: Dae Suk KIM ,  Jong Chern Lee ,  Sang Jin Byeon

Inventor： Dae Suk KIM ,  Jong Chern Lee ,  Sang Jin Byeon

IPC: H03K3/289

CPC classification number: G06F13/4247

Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

Abstract translation: 半导体装置可以包括主芯片，第一至第n从属芯片，第一至第n从属芯片ID生成单元和主芯片ID生成单元。 第1〜第n从属芯片ID生成部分分别配置在第1至第n从属芯片中并串联连接。 第一至第n从属芯片ID生成单元中的每一个被配置为向第m个操作码添加预定代码值，以生成第（m + 1）个操作代码。 主芯片ID产生单元设置在主芯片中，以响应于选择信号产生可变的第一操作码。 这里，'n'为2以上的整数，'m'为1以上且等于或小于'n'的整数。

公开(公告)号：US20120153280A1

公开(公告)日：2012-06-21

申请号：US13041003

申请日：2011-03-04

Applicant: Dae-Suk KIM ,  Jong-Chern LEE ,  Chul KIM

Inventor： Dae-Suk KIM ,  Jong-Chern LEE ,  Chul KIM

IPC: H01L23/52

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  H01L23/481 ,  H01L24/05 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

Abstract translation: 在晶圆级别检测贯通硅通孔是否具有缺陷的集成电路。 集成电路包括：半导体衬底;通孔构造成形成在半导体衬底中以从半导体衬底的表面延伸到一定深度的通硅通孔，输出焊盘和电流通路提供单元，其被配置为提供电流， 在测试模式期间，在半导体衬底和贯穿硅通孔之间流动到输出焊盘。

公开(公告)号：US20110292707A1

公开(公告)日：2011-12-01

申请号：US12948936

申请日：2010-11-18

Applicant: Chul Kim ,  Jong Chern Lee

Inventor： Chul Kim ,  Jong Chern Lee

IPC: G11C7/08 ,  G11C5/02

CPC classification number: G11C7/18 ,  G11C2207/002

Abstract: A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines.

Abstract translation: 半导体存储装置包括：包括多个存储单元的存储单元阵列; 通过位线耦合到存储单元阵列中的存储单元的位线读出放大器（BLSA）; 耦合到所述BLSA的多个本地输入/输出线; 以及耦合到本地输入/输出线并被配置为选择本地输入/输出线的一部分的开关单元。

公开(公告)号：US20110291266A1

公开(公告)日：2011-12-01

申请号：US12833436

申请日：2010-07-09

Applicant: Sin-Hyun Jin ,  Jong-Chern Lee

Inventor： Sin-Hyun Jin ,  Jong-Chern Lee

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.

Abstract translation: 具有多芯片结构的半导体集成电路包括多个层叠的半导体芯片。 半导体芯片中的至少一个包括分开形成在半导体芯片内部的第一和第二金属层，串联耦合在半导体芯片内的第一和第二金属层之间的第一内部电路，垂直形成在第二金属层上的第一金属路径 到半导体芯片的第一侧，以及通过半导体芯片从半导体芯片的第二侧形成到第一金属层的第一贯穿硅通孔。

公开(公告)号：US20110242928A1

公开(公告)日：2011-10-06

申请号：US12970792

申请日：2010-12-16

Applicant: Jae Bum KO ,  Jong Chern LEE

Inventor： Jae Bum KO ,  Jong Chern LEE

IPC: G11C8/06 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C8/04

Abstract: An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.

Abstract translation: 半导体存储装置的地址延迟电路包括：控制脉冲生成单元，被配置为在输入读取写入脉冲之后产生与时钟的预定倍数相对应的时间的控制脉冲; 以及延迟单元，被配置为当输入所述控制脉冲时输出内部地址，其中所述内部地址被输入为外部地址。

公开(公告)号：US20110211406A1

公开(公告)日：2011-09-01

申请号：US12840199

申请日：2010-07-20

Applicant: Jae Bum KO ,  Jong Chern Lee

Inventor： Jae Bum KO ,  Jong Chern Lee

IPC: G11C7/00

CPC classification number: G11C8/18

Abstract: An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address.

Abstract translation: 半导体存储装置的地址延迟电路包括控制时钟延迟块，其被配置为响应于第一输入控制信号而将时钟作为第一控制时钟接收，并且输出外部地址作为第一延迟地址; 控制时钟输入选择延迟块，被配置为响应于第二输入控制信号而将时钟作为第二控制时钟接收，响应于第一输入控制信号选择是接收外部地址还是接收第一延迟地址，并输出 选择地址作为第二个延迟地址; 以及控制时钟输入/输出选择延迟块，被配置为接收所述时钟，响应于所述第二输入控制信号选择是接收所述外部地址还是接收所述第二延迟地址，并将所选择的地址作为内部地址输出。

公开(公告)号：US20110158024A1

公开(公告)日：2011-06-30

申请号：US12650594

申请日：2009-12-31

Applicant: Dae-Suk KIM ,  Jong-Chern Lee

Inventor： Dae-Suk KIM ,  Jong-Chern Lee

IPC: G11C7/00 ,  G11C8/00 ,  G11C8/08

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40618

Abstract: A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.

Abstract translation: 半导体存储器件包括具有多个垫的存储体，地址计数单元，被配置为接收以对应于所述垫的数量的预定间隔连续地施加的自动刷新命令，并且响应于所述自动刷新命令顺序计数内部地址， 刷新命令和地址传送单元，被配置为响应于所述自动刷新命令启用所述多个垫，并且以预定的时间间隔将所述内部地址传送到所述多个垫。

公开(公告)号：US20110156767A1

公开(公告)日：2011-06-30

申请号：US12755949

申请日：2010-04-07

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03L7/0814 ,  H03L7/07

Abstract: A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.

Abstract translation: 延迟锁定环包括延迟脉冲产生单元，编码单元和延迟线。 延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。 编码单元被配置为对延迟脉冲进行编码并输出代码值。 延迟线被配置为通过代码值来延迟输入时钟，并产生延迟的锁定时钟。 延迟脉冲在与第一周期（对应于输入时钟的整数倍）和第二周期（在某个复制延迟周期）之间的差值的第三周期内具有逻辑高电平状态。

公开(公告)号：US20110156766A1

公开(公告)日：2011-06-30

申请号：US12753442

申请日：2010-04-02

Applicant: Seung-Joon AHN ,  Jong-Chern Lee

Inventor： Seung-Joon AHN ,  Jong-Chern Lee

IPC: H03L7/00 ,  H03L7/06

CPC classification number: H03L7/0816 ,  H03L7/0814

Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

Abstract translation: 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。

公开(公告)号：US20110103164A1

公开(公告)日：2011-05-05

申请号：US12647196

申请日：2009-12-24

Applicant: Jae-Woong YUN ,  Jong-Chern Lee ,  Hee-Jin Byun

Inventor： Jae-Woong YUN ,  Jong-Chern Lee ,  Hee-Jin Byun

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/40 ,  G11C2029/2602

Abstract: A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip.

Abstract translation: 半导体存储器件包括多个数据传输线，多个并行到串行转换部分，被配置为从所述多个数据传输线中的至少两个数据传输线接收串行对准和输出数据;多个数据压缩电路 被配置为接收，压缩和输出多个并行到串行转换部分中的至少两个的输出，以及多个数据输出电路，被配置为将多个数据压缩电路的各个压缩结果输出到 芯片。