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238 条记录 (耗时 0.026 秒)

    Semiconductor memory device for performing refresh operation
    81.
    发明授权
    Semiconductor memory device for performing refresh operation 有权
    用于执行刷新操作的半导体存储器件

    公开(公告)号：US07180808B2

    公开(公告)日：2007-02-20

    申请号：US10954530

    申请日：2004-09-29

    申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40622

    摘要： A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

    摘要翻译： 根据本发明的存储器件包括多个刷新模式和刷新控制器。 第一刷新模式可以分别在包括多个块和所有存储体中的每一个的多个存储体中选择一个存储器块。 此外，第一刷新模式可以针对所选择的存储块执行刷新操作。 第二刷新模式可以选择一个存储体的一部分并执行与所选存储体的数据的刷新操作。 控制器可以在刷新操作中选择第一和第二刷新模式之一。

    Needle alignment verification circuit and method for semiconductor device
    82.
    发明申请
    Needle alignment verification circuit and method for semiconductor device 有权
    针对对准验证电路及半导体器件的方法

    公开(公告)号：US20070030017A1

    公开(公告)日：2007-02-08

    申请号：US11360827

    申请日：2006-02-23

    申请人： Jong-Hyun Choi ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Young-Hun Seo

    IPC分类号： G01R31/02

    CPC分类号： G01R1/06794

    摘要： A needle alignment verification circuit includes a sensor pad, a first transmission line, a control element, a data pad, a second transmission line, and a response element. The sensor pad includes an insulation part and a conduction part. The first transmission line is electrically connected to the conduction part and to the interior of the semiconductor device. The control element asserts the first transmission line at a first logic state, and upon receiving the probe signal at the conduction part, transitions the logic state of the first transmission line to a second logic state. The second transmission line provides a predetermined signal to the data pad. The response element controls the second transmission line so that the second transmission line has the state of a verification result voltage for a misalignment state in response to the second logic state.

    摘要翻译： 针对准验证电路包括传感器焊盘，第一传输线，控制元件，数据焊盘，第二传输线和响应元件。 传感器垫包括绝缘部分和导电部分。 第一传输线电连接到导电部分和半导体器件的内部。 控制元件在第一逻辑状态下使第一传输线断言，并且在接收到导通部分的探测信号时，将第一传输线的逻辑状态转换到第二逻辑状态。 第二传输线向数据焊盘提供预定的信号。 响应元件控制第二传输线，使得第二传输线响应于第二逻辑状态具有用于不对准状态的验证结果电压的状态。

    Semiconductor memory devices and method of sensing bit line thereof
    85.
    发明申请
    Semiconductor memory devices and method of sensing bit line thereof 有权
    半导体存储器件及其位线检测方法

    公开(公告)号：US20060023537A1

    公开(公告)日：2006-02-02

    申请号：US11185351

    申请日：2005-07-20

    申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

    发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

    IPC分类号： G11C7/02

    CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

    摘要： A semiconductor memory device and a bit line sensing method thereof are disclosed. The semiconductor memory device includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor.

    摘要翻译： 公开了一种半导体存储器件及其位线检测方法。 半导体存储器件包括连接在由第一地址和反向位线访问的第一字线之间的第一存储器单元; 连接在由第二地址访问的第二字线和位线之间的第二存储器单元; 第一类型读出放大器串联连接在位线和反相位线之间，并且具有感测反向位线的第一类型第一MOS晶体管和感测位线的第一类型第二MOS晶体管，如果第一电压的第一使能信号为 应用; 串联连接在位线和反相位线之间的第二类型的第一读出放大器，并且具有检测反相位线的第二类型的第一MOS晶体管和感测位线的第二类型的第二MOS晶体管，如果第二电压的第二使能信号 其中所述第二类型的第一MOS晶体管具有比所述第二类型的第二MOS晶体管更好的感测能力; 以及第二类型的第二读出放大器，其串联连接在位线和反相位线之间，并且具有感测反转位线的第二类型的第三MOS晶体管和感测位线的第二类型的第四MOS晶体管，如果第二个 施加电压，其中第二类型的第四MOS晶体管具有比第二类型的第三MOS晶体管更好的感测能力。

    System and method for performing partial array self-refresh operation in a semiconductor memory device
    88.
    发明申请
    System and method for performing partial array self-refresh operation in a semiconductor memory device 有权
    在半导体存储器件中进行部分阵列自刷新操作的系统和方法

    公开(公告)号：US20050041506A1

    公开(公告)日：2005-02-24

    申请号：US10959804

    申请日：2004-10-06

    申请人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    发明人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

    摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

    摘要翻译： 执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个部分（例如，1 / 2,1 / 8或{分数（1/16））的一部分执行用于对存储数据进行再充电的刷新操作 在一个方面，通过（1）在自刷新操作期间通过行地址计数器控制行地址的生成来执行PASR操作，以及（2）控制自身的自身 - 刷新周期产生电路，用于调整其自刷新周期输出，在PASR操作期间以减少电流消耗的方式调整自刷新周期，另一方面，通过控制一个PASR操作来执行PASR操作 或更多行对应于自刷新操作期间的部分单元阵列的行地址，从而通过阻止存储器组的未使用块的激活来实现自刷新电流消耗的减少。

    System and method for performing partial array self-refresh operation in a semiconductor memory device
    89.
    发明授权
    System and method for performing partial array self-refresh operation in a semiconductor memory device 有权
    在半导体存储器件中进行部分阵列自刷新操作的系统和方法

    公开(公告)号：US06590822B2

    公开(公告)日：2003-07-08

    申请号：US09925812

    申请日：2001-08-09

    申请人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    发明人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    IPC分类号： G11C700

    CPC分类号： G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

    摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

    摘要翻译： 执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个所选择的存储体的一部分（例如，1/2，1/8或1/16）执行用于对存储的数据进行再充电的刷新操作 包括半导体存储器件中的单元阵列。 一方面，通过以下操作来执行PASR操作：（1）在自刷新操作期间通过行地址计数器控制行地址的生成，以及（2）控制自刷新周期发生电路以调整自刷新周期输出 由此。 调整自刷新周期，从而在PASR操作期间降低电流消耗。 在另一方面，通过在自刷新操作期间控制对应于部分单元阵列的一个或多个行地址来执行PASR操作，由此通过阻止未使用的激活来实现自刷新电流消耗的减少 一块记忆库。

    Mode selection circuit for semiconductor memory device
    90.
    发明授权
    Mode selection circuit for semiconductor memory device 有权

    公开(公告)号：US06459636B2

    公开(公告)日：2002-10-01

    申请号：US09838358

    申请日：2001-04-19

    申请人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

    发明人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

    IPC分类号： G11C700

    CPC分类号： G11C29/46

    摘要： A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.