公开(公告)号：US08537956B1

公开(公告)日：2013-09-17

申请号：US12954514

申请日：2010-11-24

Applicant: Tien Duc Pham ,  Leon Zheng ,  Sergey Shumarayev ,  Zhi Y. Wong ,  Paul B. Ekas

Inventor： Tien Duc Pham ,  Leon Zheng ,  Sergey Shumarayev ,  Zhi Y. Wong ,  Paul B. Ekas

IPC: H03D3/24

CPC classification number: H03L7/0802 ,  H03L7/1976 ,  H04J3/047 ,  H04J3/062

Abstract: A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

Abstract translation: 解复用器电路将具有不同数据速率的输入数据分离成输出数据。 锁相环电路产生具有基于第二时钟信号的频率的平均频率乘以分数非整数的第一时钟信号。 串行器电路串行化一组输出数据以响应于由锁相环电路产生的第一时钟信号之一产生串行数据信号。

公开(公告)号：US08464088B1

公开(公告)日：2013-06-11

申请号：US12915794

申请日：2010-10-29

Applicant: Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

Inventor： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F1/10

Abstract: Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair. In one embodiment, second groups of connection lines connect channels in one channel group pair to channels in other channel group pairs such that one or more channels across the channel group pairs can receive a clock signal generated by a CGB in a designated channel. These and other embodiments are described more fully in the disclosure.

Abstract translation: 公开了与用于柔性通道结合的时钟分配有关的各种方法和结构。 一个实施例提供物理介质连接（“PMA”）电路中的时钟网络，系统互连电路的特定类型或部分，被布置成成对的信道组。 在一个实施例中，每对信道组中的时钟产生电路块（“CGB”）接收多个锁相环电路（“PLL”）的输出，这些电路可被CGB选择性地用于产生PMA时钟信号。 在另一个实施例中，CGB还可以在一对信道组的信道组的信道之一中选择时钟数据恢复（“CDR”）/发送PLL电路块的输出。 在一个实施例中，第一组连接线将信道组对中的电路耦合，使得每个信道组对中的指定CGB可以向信道组对中的一个或多个信道提供时钟信号。 在一个实施例中，第二组连接线将一个信道组对中的信道与其它信道组对中的信道相连，使得跨信道组对的一个或多个信道可以接收由指定信道中的CGB产生的时钟信号。 在本公开中更全面地描述了这些和其它实施例。

公开(公告)号：US20130114663A1

公开(公告)日：2013-05-09

申请号：US13289791

申请日：2011-11-04

Applicant: Weiqi DING ,  Sergey SHUMARAYEV ,  Peng LI ,  Sriram NARAYAN

Inventor： Weiqi DING ,  Sergey SHUMARAYEV ,  Peng LI ,  Sriram NARAYAN

IPC: H03K5/159

CPC classification number: H04L25/03038 ,  H04L25/03146 ,  H04L2025/03573

Abstract: One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及一种用于数据链路的接收机电路。 接收器电路至少包括第一信号路径，第二信号路径和路径选择器电路。 第一信号路径包括第一均衡电路，第二信号路径包括第二均衡电路。 路径选择器电路被配置为选择第一和第二信号路径的一个信号路径。 还公开了其它实施例和特征。

公开(公告)号：US08385496B1

公开(公告)日：2013-02-26

申请号：US12909744

申请日：2010-10-21

Applicant: Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

Inventor： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H04L7/033

Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及一种用于集成电路中的接收机的偏移抵消的方法。 接收机设置为相位检测器偏移消除模式，以便确定相位检测器的偏移消除设置。 偏移消除设置被应用于相位检测器。 然后将接收机设置为接收器 - 驱动器偏移消除模式，以便确定接收器驱​​动器的偏移消除设置。 该偏移消除设置被应用于接收器驱动器。 另一实施例涉及被配置为执行接收机偏移消除的集成电路。 该集成电路包括被配置为接收差分输入信号的接收器驱动器，包括多个锁存器的相位检测器，校准控制器，电压源以及第一和第二对开关。 还公开了其它实施例，方面和特征。

公开(公告)号：US08319564B2

公开(公告)日：2012-11-27

申请号：US12748261

申请日：2010-03-26

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC: H03B5/12 ,  H03L1/00

CPC classification number: H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract translation: 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

公开(公告)号：US08208523B2

公开(公告)日：2012-06-26

申请号：US13079420

申请日：2011-04-04

Applicant: Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

Inventor： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC: H03H7/30

CPC classification number: H04L25/03885

Abstract: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Abstract translation: 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US08194724B1

公开(公告)日：2012-06-05

申请号：US12823783

申请日：2010-06-25

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

IPC: H03H7/30 ,  H03H7/40

CPC classification number: H04L25/03044 ,  H04L2025/03356 ,  H04L2025/03579 ,  H04L2025/03783

Abstract: A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.

Abstract translation: 可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。 均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否 （5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

公开(公告)号：US20120126896A1

公开(公告)日：2012-05-24

申请号：US12954090

申请日：2010-11-24

Applicant: Sriram NARAYAN ,  Xiaoyan SU ,  Sergey SHUMARAYEV

Inventor： Sriram NARAYAN ,  Xiaoyan SU ,  Sergey SHUMARAYEV

IPC: H03F3/45 ,  H03F1/00

CPC classification number: H03F1/30 ,  H03F3/45197 ,  H03F3/45973 ,  H03F2200/375 ,  H03F2200/405 ,  H03F2203/45354 ,  H03F2203/45374

Abstract: One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及配置有偏移消除环路的连续时间电路。 连续时间电路包括多级放大器链，包括第一放大级和最后的放大级，以及偏移消除环。 偏移消除环路被配置为接收最后的放大器级的输出并且向第一放大器级提供偏移校正电压信号。 偏移补偿环路可以产生一个主极点和单个后续寄生极点，以便具有更大的稳定性，并且可以有利地在较高频率处实现响应幅度的二阶滚降。 还公开了其它实施例，方面和特征。

公开(公告)号：US08081723B1

公开(公告)日：2011-12-20

申请号：US12082343

申请日：2008-04-09

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran

IPC: H04L7/00

CPC classification number: H04L7/048 ,  H04L1/205 ,  H04L7/033

Abstract: Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.

Abstract translation: 用于确定高速串行数据信号的眼睛的至少部分宽度的方法和装置使用在该信号上操作的时钟和数据恢复电路，以产生与数据信号具有第一相位关系的第一时钟信号。 第一时钟信号用于产生第二时钟信号，其相位可相对于第一相位被可控地偏移。 第二时钟信号用于以不同量的相移对数据信号进行采样，例如直到错误检查电路检测到所得样本中的数据错误超过这种错误的可接受的阈值。 引起超过阈值的相移量可用作测量眼睛宽度的基础。

公开(公告)号：US20110234331A1

公开(公告)日：2011-09-29

申请号：US12748261

申请日：2010-03-26

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC: H03B5/12 ,  H01F5/00

CPC classification number: H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract translation: 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。