公开(公告)号：US20010014019A1

公开(公告)日：2001-08-16

申请号：US09781485

申请日：2001-02-12

Applicant: U.S. PHILIPS CORPORATION

Inventor： Simon H.A. Begemann

IPC: F21V029/00

CPC classification number: F21V29/67 ,  F21K9/232 ,  F21S8/036 ,  F21V3/00 ,  F21V23/04 ,  F21V29/677 ,  F21V29/70 ,  F21V29/83 ,  F21W2131/10 ,  F21Y2107/40 ,  F21Y2113/17 ,  F21Y2115/10 ,  Y10S362/80 ,  Y10S362/802

Abstract: The invention relates to a LED lamp comprising a gear column which is connected, at its first end, to a lamp cap and, at its other end, to a substrate. Said substrate comprises a number of LEDs. According to the invention, said substrate is provided with a regular polyhedron of at least four planes, said planes comprising at least one LED having a luminous flux of at least 5 lm. The gear column also comprises heat-dissipating means which interconnect the substrate and the lamp cap. A continuous and regular illumination with a high luminous flux can be obtained using a LED lamp of this type.

Abstract translation: 本发明涉及一种LED灯，其包括齿轮柱，该齿轮柱在其第一端处连接到灯帽，并且在另一端连接到基板。 所述衬底包括多个LED。 根据本发明，所述基板设置有至少四个平面的正多面体，所述平面包括至少一个具有至少5lm的光通量的LED。 齿轮柱还包括将衬底和灯帽相互连接的散热装置。 可以使用这种LED灯获得具有高光通量的连续且规则的照明。

公开(公告)号：US20010013791A1

公开(公告)日：2001-08-16

申请号：US09819287

申请日：2001-03-28

Applicant: U.S. Philips Corporation

Inventor： Johannes P.M. Van Lammeren ,  Taco Zwemstra

IPC: G01R031/26

CPC classification number: G01R31/3004

Abstract: The method for inspecting an integrated circuit comprising a plurality of sub-circuits includes the determination of the supply current into at least one of the sub-circuits. This supply current is determined, while the other sub-circuits are operational, by measuring the voltage over a segment of the supply line through which this supply current flows. This supply line contains no additional components to facilitate the measuring of the voltage.

Abstract translation: 用于检查包括多个子电路的集成电路的方法包括确定进入至少一个子电路的电源电流。 确定该供电电流，而其他子电路可操作，通过测量该电源电流通过的电源线段上的电压。 该电源线不包含额外的组件，以便于测量电压。

公开(公告)号：US20010013613A1

公开(公告)日：2001-08-16

申请号：US09781498

申请日：2001-02-12

Applicant: U.S. PHILIPS CORPORATION

Inventor： Godefridus A.M. Hurkx ,  Rob Van Dalen

IPC: H01L029/80 ,  H01L031/112

CPC classification number: H01L29/408 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device has first and second opposed major surfaces (10a and 10b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 130) with the first region (11) and separates the first region (11) from the first major surface (10a) while the third region (14) separates the first region (11) from the second major surface (10b). A plurality of semi-insulating or resistive paths (21) are dispersed within the first region (1null) such that each path extends through the first region from the second to the third region. In use of the device when a reverse biasing voltage is applied across the rectifying junction (13 or 130) an electrical potential distribution is generated along the resistive paths (21) which causes a depletion region in the first region (11) to extend through the first region (11) to the third region (14) to increase the reverse breakdown voltage of the device. The device may be, for example a pn-n diode in which case the second region is a semiconductive region of the opposite conductivity type to the first region or a Schottky diode in which case the second region (120) forms a Schottky contact with the first region.

Abstract translation: 半导体器件具有第一和第二相对的主表面（10a和10b）。 半导体第一区域（11）设置在第二（12或120）和第三（14）区域之间，使得第二区域（12或120）与第一区域（11）形成整流结（13或130） 所述第一区域（11）从所述第一主表面（10a）移动，而所述第三区域（14）将所述第一区域（11）与所述第二主表面（10b）分离。 多个半绝缘或电阻路径（21）分散在第一区域（1'）内，使得每个路径从第二区域延伸穿过第一区域。 当跨越整流结（13或130）施加反向偏置电压时，在使用该器件时，电阻分布沿着电阻通道（21）产生，这导致第一区域（11）中的耗尽区延伸通过 第一区域（11）到第三区域（14），以增加器件的反向击穿电压。 器件可以是例如pn-n二极管，在这种情况下，第二区域是与第一区域相反的导电类型的半导体区域或肖特基二极管，在这种情况下，第二区域（120）形成肖特基接触 第一区。

公开(公告)号：US20010012757A1

公开(公告)日：2001-08-09

申请号：US09797085

申请日：2001-03-01

Applicant: U.S. Philips Corporation

Inventor： Kevin R. Boyle

IPC: H04Q007/20 ,  H04B007/00

CPC classification number: H04W84/20 ,  H04W84/18 ,  H04W92/02

Abstract: In an ad-hoc radio communication system comprising a plurality of stations (100) formed into at least one network (102a,102b), each station (100) is assigned a rank representative of its suitability for performing the role of master station in a network (102a). The rank may for example be assessed depending on the performance of the station's antenna (204) or its access to mains power. It is arranged that the station (100) having the highest rank in a network (102a,102b) performs the role of master for that network, thereby improving the efficiency of communication in the network.

Abstract translation: 在包括形成在至少一个网络（102a，102b）中的多个站（100）的自组织无线电通信系统中，每个站（100）被分配代表其适用性的等级，以在主站中执行主站的作用 网络（102a）。 例如，可以根据站的天线（204）的性能或其对主电源的访问来评估等级。 布置在网络（102a，102b）中具有最高等级的站（100）执行该网络的主站的作用，从而提高网络中的通信效率。

公开(公告)号：US20010007568A1

公开(公告)日：2001-07-12

申请号：US09749733

申请日：2000-12-27

Applicant: U.S. PHILIPS CORPORATION

Inventor： Octavius J. Morris

IPC: H04J003/24

CPC classification number: H04N21/4344 ,  G11B27/034 ,  G11B27/10 ,  G11B27/105 ,  G11B27/107 ,  G11B27/3027 ,  G11B2220/20 ,  G11B2220/90 ,  H04N5/775 ,  H04N9/8042 ,  H04N21/23406 ,  H04N21/4147 ,  H04N21/44004

Abstract: A digital video recorder or similar apparatus implements a method of converting an input data stream having an MPEG-2 Program Stream (PS) format into an output data stream having an MPEG-2 Transport Stream (TS) format. The input data stream (PS) includes data of at least first and second elementary data streams (404, 406) formed and multiplexed in compliance with a PS decoder model. A scheduler (412) within the apparatus inhibits reading of a further data block from the input stream when, in the absence of a vacancy for data of an audio elementary stream within a target decoder model (418), a clock reference (SCR) of said input data stream advances beyond a clock reference of said output data stream by a predetermined waiting threshold.

Abstract translation: 数字视频记录器或类似装置实现将具有MPEG-2节目流（PS）格式的输入数据流转换为具有MPEG-2传输流（TS）格式的输出数据流的方法。 输入数据流（PS）包括根据PS解码器模型形成和复用的至少第一和第二基本数据流（404,406）的数据。 当在目标解码器模型（418）内没有用于音频基本流的数据的空缺的情况下，该设备内的调度器（412）禁止从输入流读取另外的数据块，时钟参考（SCR） 所述输入数据流超过所述输出数据流的时钟参考预定等待阈值。

公开(公告)号：US20010001022A1

公开(公告)日：2001-05-10

申请号：US09730678

申请日：2000-12-06

Applicant: U.S. PHILIPS CORPORATION

Inventor： John R. Kinghorn

IPC: H04N005/91 ,  H04N007/04 ,  H04N007/06 ,  H04N007/08 ,  H04N007/52

CPC classification number: H04N5/9206 ,  G11B15/087 ,  G11B23/0305 ,  G11B27/107 ,  G11B27/11 ,  G11B27/3054 ,  G11B27/328 ,  G11B27/34 ,  G11B2220/41 ,  G11B2220/65 ,  G11B2220/90

Abstract: A tape indexing arrangement for video recorders records the index on the tape using standard broadcast teletext codes. When a tape is inserted the contents list it contains is written onto an index RAM in the recorder (200). When a new programme is recorded a programme identification is generated from PDC or EPG data (202). At a suitable later time the contents of the index RAM are recorded on the tape (204).

Abstract translation: 视频录像机的磁带索引装置使用标准广播图文代码在磁带上记录索引。 当插入磁带时，其包含的内容列表被写入记录器（200）中的索引RAM。 当记录新节目时，从PDC或EPG数据（202）生成节目标识。 在适当的较后时间，索引RAM的内容被记录在磁带（204）上。

公开(公告)号：US20010000138A1

公开(公告)日：2001-04-05

申请号：US09730432

申请日：2000-12-05

Applicant: U.S. Philips Corporation

Inventor： Nicolas Bailleul

IPC: H04J003/00

CPC classification number: H04N19/00 ,  H04N19/192 ,  H04N19/40 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N21/23406 ,  H04N21/2343 ,  H04N21/234354 ,  H04N21/23608 ,  H04N21/2401

Abstract: A data stream (DS) comprises a time multiplex of coded data (D) and control data (C). The data stream (DS) may be, for example, of the MPEG type representing a sequence of pictures. The coded data (D) is transcoded (T) so as to obtain transcoded data (DT) which differs in size from the coded data (D). The control data (C) is adapted for the transcoded data (DT) so as to obtain adapted control data (CA) which does not substantially differ in size from the control data (C). The transcoded data (DT) and the adapted control data (CA) are written into a transcoder output buffer (TOB) and read from the transcoder output buffer (TOB) so as to obtain a transcoded data stream (DST). This allows an efficient use of a transmission channel via which the transcoded data stream (DST) is to be transmitted and, consequently, it allows a satisfactory transcoding quality. A size adjustment of the transcoded data (DT) on the basis of the amount of data contained in the transcoder output buffer (TOB) and control codes (CC) contained in the data stream (DS) further contributes to a satisfactory transcoding quality.

公开(公告)号：US20040095533A1

公开(公告)日：2004-05-20

申请号：US10705318

申请日：2003-11-10

Applicant: U.S. PHILIPS CORPORATION

Inventor： Sjoerd Stallinga ,  Peter Van De Witte

IPC: G02F001/1335

CPC classification number: G02F1/133753 ,  G02F2001/133757 ,  G02F2413/15

Abstract: In a normally black double cell, grey scale enhancement is obtained by dividing pixels in the driving cell into sub-pixels which are rotated preferably through 180null with respect to each other.

Abstract translation: 在通常黑色的双单元格中，通过将驱动单元中的像素相对于彼此优选地旋转180°的子像素来获得灰度增强。

公开(公告)号：US20040014274A1

公开(公告)日：2004-01-22

申请号：US10462846

申请日：2003-06-16

Applicant: U.S. PHILIPS CORPORATION

Inventor： Nicole Anne Helena Freddy Wils ,  Michiel Slotboom ,  Franciscus Petrus Widdershoven

IPC: H01L021/8238

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device comprises a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11,25). The gate dielectric (11,25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure (8).

Abstract translation: 半导体器件包括半导体本体（1），其在表面（2）处设置有包括源极（3）和漏极（4）的非易失性存储单元，以及存取栅极（14），其电绝缘 从包括控制栅极（9）的栅极结构（8），栅极结构（8）通过栅极电介质（11,25）与半导体本体（1）电绝缘。 栅极电介质（11,25）设置有电荷存储区域，其中可以存储电荷形式的数据。 进入门（14）具有基本上平行于半导体本体（1）的表面（2）延伸的基本平坦的表面部分（17），并且具有块状形状，该块形状抵靠栅极结构（8）而不重叠 门结构（8）。

公开(公告)号：US20030191999A1

公开(公告)日：2003-10-09

申请号：US10407088

申请日：2003-04-04

Applicant: U.S. PHILIPS CORPORATION

Inventor： Richard Petrus Kleihorst ,  Renatus Josephus Van Der Vleuten ,  Nico Frits Benschop ,  Geeke Muurling

IPC: G06F011/00 ,  G01R031/28

CPC classification number: G06F11/085 ,  H03M13/00

Abstract: Errors are corrected that occur in the operation of a combinatorial logic circuit in an integrated circuit. The combinatorial circuit computes a vector of intermediate signals from the input signal. The combinatorial logic circuit is designed so that, when the combinatorial logic circuit operates without error, the vector belongs to an error correcting code, not being a repetition code. The combinatorial logic circuit comprises combinatorial logic sections, each for computing a respective one of the intermediate signals independently from the other sections. An error correction circuit computes an output signal from the vector, with a computation that maps erroneous vectors to the output signal for a nearest correct vector from the error correcting code when these erroneous vectors differ from the correct vector in less than a predetermined number of the intermediate signals.