公开(公告)号：US20050156208A1

公开(公告)日：2005-07-21

申请号：US10955349

申请日：2004-09-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/665 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/785

Abstract: Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least one of the two silicides is an alloy silicide. An etch stop layer may overlay at least one of the silicide regions.

Abstract translation: 提供半导体器件及其制造方法。 在一个示例中，半导体器件包括使用第一硅化物类型形成在衬底上的有源区和使用另一种硅化物类型形成在衬底上的另一有源区。 两种硅化物类型不同，并且两种硅化物中的至少一种是合金硅化物。 蚀刻停止层可覆盖至少一个硅化物区域。

公开(公告)号：US20050151166A1

公开(公告)日：2005-07-14

申请号：US10835100

申请日：2004-04-29

Applicant: Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a metal contact is provided. In the preferred embodiment, a metal contact is provided through an interlayer dielectric and is in electrical contact with a metal structure, such as a metal gate electrode of a transistor. A conductive layer is provided between the metal contact and the metal structure. The conductive layer provides one or more of a barrier layer, an adhesion layer, or an etch stop layer. The conductive layer is preferably an elemental metal, metal alloy, metal nitride, metal oxide, or a combination thereof. In an alternative embodiment, the conductive layer is formed of polysilicon.

Abstract translation: 提供具有金属接触的半导体器件。 在优选实施例中，通过层间电介质提供金属接触，并与诸如晶体管的金属栅电极的金属结构电接触。 在金属接触件和金属结构之间设置导电层。 导电层提供阻挡层，粘合层或蚀刻停止层中的一个或多个。 导电层优选为元素金属，金属合金，金属氮化物，金属氧化物或其组合。 在替代实施例中，导电层由多晶硅形成。

公开(公告)号：US06911379B2

公开(公告)日：2005-06-28

申请号：US10379873

申请日：2003-03-05

Applicant: Yee-Chia Yeo ,  Wen-Chin Lee

Inventor： Yee-Chia Yeo ,  Wen-Chin Lee

IPC: H01L21/762 ,  H01L29/10 ,  H01L29/786 ,  H10L21/20 ,  H10L21/36

CPC classification number: H01L29/7842 ,  H01L21/76254 ,  H01L29/1054 ,  H01L29/78654

Abstract: A method of forming a strained-silicon-on-insulator substrate is disclosed. A target wafer includes an insulator layer on a substrate. A donor wafer includes a bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon and a strained silicon layer formed on the bulk semiconductor substrate. The top surface of the donor wafer is bonded to the top surface of the target wafer. The strained silicon layer is then separated from the donor wafer so that the strained silicon layer adheres to the target wafer. The bond between the strained silicon layer and the target wafer can then be strengthened.

Abstract translation: 公开了一种形成绝缘体上的应变硅衬底的方法。 目标晶片在基板上包括绝缘体层。 施主晶片包括具有不同于硅的晶格常数的晶格常数的体半导体衬底和在体半导体衬底上形成的应变硅层。 施主晶片的顶表面结合到目标晶片的顶表面。 然后将应变硅层从施主晶片分离，使得应变硅层粘附到目标晶片。 然后可以加强应变硅层和目标晶片之间的结合。

公开(公告)号：US20050116360A1

公开(公告)日：2005-06-02

申请号：US10896270

申请日：2004-07-21

Applicant: Chien-Chao Huang ,  Fu-Liang Yang ,  Mickey Ken ,  Chenming Hu ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chih-Hsin Ko

Inventor： Chien-Chao Huang ,  Fu-Liang Yang ,  Mickey Ken ,  Chenming Hu ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chih-Hsin Ko

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L31/0328

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

Abstract: A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.

Abstract translation: 提供互补的FET和制造方法。 互补FET使用具有<100>晶体取向的表面层的衬底。 通过硅化源极/漏极区域，拉伸应力膜，浅沟槽隔离层，层间电介质等添加了提高NMOS FET的性能的拉伸应力。

公开(公告)号：US20050093018A1

公开(公告)日：2005-05-05

申请号：US10699574

申请日：2003-10-31

Applicant: Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

Abstract translation: 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US10546964B2

公开(公告)日：2020-01-28

申请号：US13677361

申请日：2012-11-15

Applicant: Shih-Wei Chen ,  Wen-Chin Lee ,  Wen-Tsai Yen ,  Chung-Hsien Wu ,  Kuan-Chu Chen

Inventor： Shih-Wei Chen ,  Wen-Chin Lee ,  Wen-Tsai Yen ,  Chung-Hsien Wu ,  Kuan-Chu Chen

IPC: H01L31/032 ,  H01L31/0749 ,  H01L31/0392 ,  H01L31/0224

Abstract: A solar cell with a molybdenum back electrode layer and a molybdenum selenide ohmic contact layer over the molybdenum back electrode, is provided. The molybdenum selenide layer includes an accurately controlled thickness. A distinct interface exists between the molybdenum back electrode layer and the molybdenum silicide layer. The molybdenum silicide layer is produced by forming a molybdenum layer or a molybdenum nitride layer or a molybdenum oxide layer over an initially formed molybdenum layer such that an interface exists between the two layers. A selenization and sulfurization process is carried out to selectively convert the molybdenum-containing layer to molybdenum selenide but not the original molybdenum back electrode layer which remains as a molybdenum layer.

公开(公告)号：US08536619B2

公开(公告)日：2013-09-17

申请号：US11702390

申请日：2007-02-05

Applicant: Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate.

Abstract translation: 半导体结构包括具有顶表面的半导体衬底; 半导体衬底上的栅极堆叠; 以及半导体衬底中的紧邻栅叠层的应力器。 所述应力器至少包括具有比所述半导体衬底的顶表面低的第一顶表面的第一部分。

公开(公告)号：US20130133732A1

公开(公告)日：2013-05-30

申请号：US13307025

申请日：2011-11-30

Applicant: Hsuan-Sheng YANG ,  Wen-Chin LEE

Inventor： Hsuan-Sheng YANG ,  Wen-Chin LEE

IPC: H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/022425 ,  H01L31/03923 ,  H01L31/0465 ,  H01L31/0749 ,  Y02E10/541

Abstract: A thin film solar cell and process for forming the same. The solar cell includes a bottom electrode, semiconductor light absorbing layer, and top electrode. Interconnects may be formed between the top and bottom electrodes by electrochemical plating of conductive materials in recessed regions formed between the electrodes. In some embodiments, the conductive materials may be optically opaque metals having non-light transmissive properties. The interconnects are highly conductive and minimize the thickness of the top electrode layer, thereby enhancing light transmission and cell energy conversion performance.

Abstract translation: 薄膜太阳能电池及其形成方法。 太阳能电池包括底电极，半导体光吸收层和顶电极。 可以通过在形成在电极之间的凹陷区域中的导电材料的电化学电镀，在顶部和底部电极之间形成互连。 在一些实施例中，导电材料可以是具有不透光性质的光学不透明金属。 互连是高导电性的，并使顶部电极层的厚度最小化，从而提高光透射率和电池能量转换性能。

公开(公告)号：US08236658B2

公开(公告)日：2012-08-07

申请号：US12477757

申请日：2009-06-03

Applicant: Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

Abstract translation: 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。

公开(公告)号：US08154107B2

公开(公告)日：2012-04-10

申请号：US11703365

申请日：2007-02-07

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L23/58

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

Abstract translation: 具有被超应力层覆盖的至少一个晶体管的半导体器件及其制造方法。 在NMOS器件中，超应力层包括源极和漏极区域上的拉伸应力膜，以及多个区域上的压应力膜。 在PMOS器件中，超应力层包括源极和漏极区域上的压缩应力膜和在多个区域上的拉伸应力膜。 在优选实施例中，半导体器件包括PMOS晶体管和形成CMOS器件并被超压应力层覆盖的NMOS晶体管。