公开(公告)号：US20070189068A1

公开(公告)日：2007-08-16

申请号：US11560223

申请日：2006-11-15

Applicant: Yeong-Taek Lee

Inventor： Yeong-Taek Lee

IPC: G11C16/06

CPC classification number: G11C11/404 ,  G11C11/4091 ,  G11C2211/4016

Abstract: A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating body, the reference memory cell coupled to a reference word line, a second bit line, and a second source line, a first isolation gate portion configured to selectively transmit a signal between the first bit line and at least one of a sense bit line and an inverted sense bit line, a second isolation gate portion configured to selectively transmit a signal between the second bit line and at least one of the sense bit lines, and a sense amplifier configured to amplify voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels.

Abstract translation: 一种具有第一存储单元阵列块的半导体存储器件，包括具有浮体的存储单元，耦合到字线的存储单元，第一位线和第一源极线，包括参考存储器的第二存储单元阵列块 具有浮体的单元，耦合到参考字线的参考存储单元，第二位线和第二源极线，第一隔离栅极部分，被配置为选择性地在第一位线和第一位线之间的信号 感测位线和反相感测位线，第二隔离栅极部分，被配置为选择性地在第二位线和感测位线中的至少一个之间传输信号;以及读出放大器，被配置为放大感测位线的电压， 反向感测位线到第一和第二感测放大电压电平。

公开(公告)号：US20070159903A1

公开(公告)日：2007-07-12

申请号：US11546421

申请日：2006-10-12

Applicant: Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

Inventor： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

IPC: G11C7/02

CPC classification number: G11C11/405 ,  G11C7/065 ,  G11C11/4091 ,  G11C2211/4016

Abstract: In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines.

Abstract translation: 一方面，提供了包括互补的第一和第二位线的半导体存储器件，包括分别耦合到互补的第一和第二位线的互补的第一和第二浮体晶体管无电容器存储器单元的单元存储单元，以及电压读出放大器 耦合在互补的第一和第二位线之间，互补的第一和第二位线放大互补的第一和第二位线之间的电压差。

公开(公告)号：US20070139994A1

公开(公告)日：2007-06-21

申请号：US11637519

申请日：2006-12-12

Applicant: Ki-whan Song ,  Yeong-taek Lee

Inventor： Ki-whan Song ,  Yeong-taek Lee

IPC: G11C11/24

CPC classification number: G11C11/24

Abstract: A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an open bit line structure; a plurality of memory cells each of which is connected to each of the word lines and each of the bit lines and stores at least two bits of data; and a plurality of sense amplifiers, each of which amplifies a voltage difference between the bit lines, the bit lines being located at opposite sides of each of the plurality of sense amplifiers.

Abstract translation: 公开了一种具有开放位线结构的多级动态存储器件。 多级动态存储装置包括多个字线; 设置在开放位线结构中的多个位线; 多个存储单元，每个存储单元连接到每个字线和每个位线，并存储至少两位数据; 以及多个读出放大器，每个读出放大器放大位线之间的电压差，位线位于多个读出放大器的每一个的相对侧。

公开(公告)号：US20060034127A1

公开(公告)日：2006-02-16

申请号：US11250720

申请日：2005-10-14

Applicant: Dong-Hwan Kim ,  Yeong-Taek Lee

Inventor： Dong-Hwan Kim ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

Abstract: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

公开(公告)号：US20050117378A1

公开(公告)日：2005-06-02

申请号：US10977703

申请日：2004-10-28

Applicant: Hyun-Chul Cho ,  Yeong-Taek Lee

Inventor： Hyun-Chul Cho ,  Yeong-Taek Lee

IPC: G11C16/06 ,  G11C5/06 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0483 ,  G11C16/24

Abstract: According to some embodiments, a nonvolatile semiconductor memory device includes high voltage circuits that prevent high voltages, which are applied to bitlines during an erase operation, from being applied to low voltage circuits that are operable with low voltages. Each high voltage circuit includes a first switching circuit for selectively isolating the low voltage circuit from the bitlines, and a second switching circuit for inhibiting a leakage current to the low voltage circuit from the bitlines. The second switching circuit is connected between the first switching circuit and the low voltage circuit.

Abstract translation: 根据一些实施例，非易失性半导体存储器件包括防止在擦除操作期间施加到位线的高电压被施加到可以以低电压操作的低电压电路的高电压电路。 每个高压电路包括用于选择性地将低压电路与位线隔离的第一开关电路和用于抑制从位线到低压电路的漏电流的第二开关电路。 第二开关电路连接在第一开关电路和低电压电路之间。

公开(公告)号：US06751124B2

公开(公告)日：2004-06-15

申请号：US10255214

申请日：2002-09-26

Applicant: Yeong-Taek Lee

Inventor： Yeong-Taek Lee

IPC: G11C700

CPC classification number: G11C16/10 ,  G11C16/24 ,  G11C16/30

Abstract: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages. A first stage pre-charges all bit lines via PMOS pull-up, and the second stage uses the latches to discharge or leave charged the selected bit lines depending on respective data bits being stored. The gate voltages of NMOS transistors in the programming circuitry can be controlled to reduce noise caused by discharging selected bit lines through the latches.

Abstract translation: 具有屏蔽位线结构的NAND EEPROM降低了由于充电或放电位线而导致的电源电压和接地噪声。 EEPROM具有连接到虚拟电源节点的PMOS上拉晶体管和NMOS下拉晶体管。 用于对位线进行充电或放电的控制电路控制PMOS或NMOS晶体管的栅极电压，以便通过虚拟电源节点对位线充电或放电时限制峰值电流。 特别地，控制电路以非饱和模式操作PMOS或NMOS晶体管以限制电流。 一个这样的控制电路产生电流镜或施加参考电压来控制栅极电压。 编程方法通过经由具有受控栅极电压的PMOS上拉晶体管对未选择的位线进行预充电来建立位线，同时编程电路中的锁存器根据存储的相应数据位对所选择的位线进行充电或放电。 另一个位线设置包括两个阶段。 第一级通过PMOS上拉对所有位线进行预充电，第二级根据存储的相应数据位使用锁存器对所选位线进行放电或放电。 可以控制编程电路中的NMOS晶体管的栅极电压，以减少通过锁存器放电所选位线所引起的噪声。

公开(公告)号：US06735116B2

公开(公告)日：2004-05-11

申请号：US10322268

申请日：2002-12-17

Applicant: Yeong-Taek Lee ,  Young-ho Lim

Inventor： Yeong-Taek Lee ,  Young-ho Lim

IPC: G11C1604

CPC classification number: G11C16/08 ,  G11C8/12 ,  G11C2216/14

Abstract: A NAND-type flash memory device includes a plurality of row selectors each corresponding to memory blocks of each mat therein. Each of the row selectors selects a corresponding memory block in response to block selection information. A decoding circuit and a register are supplied to each of the row selectors. The decoding circuit generates a block selection signal in response to the block selection information, and the register stores an output of the decoding circuit when a latch signal of a corresponding mat is activated. According to the above row selection construction, all mats or a part of memory blocks can be selected at the same time.

Abstract translation: NAND型闪速存储器件包括多个行选择器，每个行选择器对应于其中每个垫的存储块。 每个行选择器响应于块选择信息选择相应的存储器块。 解码电路和寄存器被提供给每个行选择器。 解码电路响应于块选择信息产生块选择信号，并且当对应的片的锁存信号被激活时，寄存器存储解码电路的输出。 根据上述行选择结构，可以同时选择所有的垫或一部分存储块。

公开(公告)号：US06611460B2

公开(公告)日：2003-08-26

申请号：US10131424

申请日：2002-04-22

Applicant: Yeong-Taek Lee ,  Young-Ho Lim

Inventor： Yeong-Taek Lee ,  Young-Ho Lim

IPC: G11C1604

CPC classification number: G11C16/12 ,  G11C16/0483

Abstract: A nonvolatile semiconductor memory device of the present invention has a well voltage detecting circuit. The well voltage detecting circuit detects whether a pocket p-type well voltage is equal to or is lower than a detection voltage (e.g., 0.1V) and outputs a detection signal at a high or low level. When the pocket p-type well voltage is identical to or lower than the detection voltage, a word line select signal generating circuit generates row select signals of respective rows in response to the detection signal. With this device, in case a well voltage of the pocket p-type well is increased due to applying a voltage into an unselected bit line, program and pass voltages are supplied to word lines at a point of time when the increased well voltage becomes lower than the detection voltage of the well voltage detecting circuit.

公开(公告)号：US06473344B2

公开(公告)日：2002-10-29

申请号：US09952515

申请日：2001-09-13

Applicant: Hyung-Gon Kim ,  Yeong-Taek Lee

Inventor： Hyung-Gon Kim ,  Yeong-Taek Lee

IPC: G11C1604

CPC classification number: G11C29/12 ,  G11C8/08

Abstract: A semiconductor memory device includes a select signal generator, a wordline voltage generator, and a switch circuit. During a test operation mode, the device determine whether a wordline voltage has required level. The select signal generator activates one of select signals each corresponding to the other wordline voltages responsive to external select code signals. The external select code signals appoint an external instruction signal representative and appoint other wordline voltages used in the memory device. The wordline voltage generator generates a wordline voltage corresponding to the activated select signal out. The switch circuit transfers the wordline voltage outputted from the wordline voltage generator to a pad connected to an external pin.

Abstract translation: 半导体存储器件包括选择信号发生器，字线电压发生器和开关电路。 在测试操作模式期间，设备确定字线电压是否具有所需的电平。 响应于外部选择码信号，选择信号发生器激活每个对应于其它字线电压的选择信号之一。 外部选择代码信号指定外部指令信号代表并指定在存储器件中使用的其它字线电压。 字线电压发生器产生与所激活的选择信号相对应的字线电压。 开关电路将从字线电压发生器输出的字线电压传送到连接到外部引脚的焊盘。

公开(公告)号：US5504715A

公开(公告)日：1996-04-02

申请号：US343949

申请日：1994-11-17

Applicant: Yeong-Taek Lee ,  Jong-Hyun Choi

Inventor： Yeong-Taek Lee ,  Jong-Hyun Choi

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/00

CPC classification number: G11C8/08

Abstract: A word line loading compensating circuit compensates a word line boosted voltage level changed in accordance with a word line loading. A word line boosting circuit outputs a word line boosted voltage boosted over a power supply voltage input from the exterior of a chip, so as to boost a voltage of the word line connected to the memory cell array. A row decoder is connected to the word line boosted voltage output from the word line boosting circuit and selects a memory cell from an array of memory cells in correspondence with a predetermined row address signal. A capacitor connected between the word line boosted voltage and the row decoder stores a charge from the word line boosted voltage. A variable connecting device connects the word line boosted voltage to the capacitor before the word line boosted voltage reaches a saturation level, and cuts off the word line boosted voltage from the capacitor after the word line boosted voltage reaches the saturation level. A delay device inputs the word line boosted voltage, delays the input word line boosted voltage during the arrival time of the saturation level, and generates a delay output signal which controls the variable connecting device. A discharging device is controlled by the delay output signal and discharges the charge stored in the capacitor to ground after the word line boosted voltage reaches the saturation level.

Abstract translation: 字线负载补偿电路补偿根据字线负载而改变的字线升压电压电平。 字线升压电路输出从芯片外部输入的电源电压升压的字线升压电压，以提高连接到存储单元阵列的字线的电压。 行解码器连接到从字线升压电路输出的字线升压电压，并根据预定行地址信号从存储器单元阵列中选择存储单元。 连接在字线升压电压和行解码器之间的电容器存储来自字线升压电压的电荷。 可变连接装置在字线升压电压达到饱和电平之前将字线升压电压连接到电容器，并且在字线升压电压达到饱和电平后，切断来自电容器的字线升压电压。 延迟装置输入字线升压电压，在饱和电平到达时延迟输入字线升压电压，并产生控制可变连接装置的延迟输出信号。 放电装置由延迟输出信号控制，并且在字线升压电压达到饱和电平后，将存储在电容器中的电荷放电到地。