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    Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection
    81.
    发明申请
    Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection 审中-公开
    具有基于误码率检测的码率选择的ECC编码和解码电路的数据处理系统

    公开(公告)号：US20100241928A1

    公开(公告)日：2010-09-23

    申请号：US12716793

    申请日：2010-03-03

    Applicant: Jaehong Kim ,  Yong June Kim ,  Junjin Kong ,  Seung-Hwan Song

    Inventor： Jaehong Kim ,  Yong June Kim ,  Junjin Kong ,  Seung-Hwan Song

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: H03M13/618 ,  G06F11/1012 ,  H03M13/13 ,  H03M13/353 ,  H03M13/3738 ,  H03M13/6356 ,  H03M13/6362

    Abstract: A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data.

    Abstract translation: 数据处理系统包括纠错（ECC）编码电路，集成电路存储器和码率控制电路。 ECC编码电路被配置为响应于码率选择信号，在操作期间选择性地应用多个唯一ECC码率来写入由数据处理系统接收的数据，以将写入数据转换为编码数据。 集成电路存储器包括多个存储区域。 这些存储区域被配置为从ECC编码电路接收编码数据的相应部分。 码率控制电路被配置为产生码率选择信号。 该码率选择信号具有指定应用于写入数据的各个部分的相应的ECC码率的值。

    Memory device and memory programming method
    82.
    发明申请
    Memory device and memory programming method 有权
    存储器和存储器编程方法

    公开(公告)号：US20090296466A1

    公开(公告)日：2009-12-03

    申请号：US12385705

    申请日：2009-04-16

    Applicant: Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

    Inventor： Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

    IPC: G11C16/02 ,  G11C16/06

    CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621

    Abstract: Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.

    Abstract translation: 提供的是存储器件和存储器编程方法。 存储器设备可以包括：包括多个存储器单元的多位单元阵列; 提取每个存储单元的状态信息的控制器，将多个存储单元划分为第一组和第二组，将第一验证电压分配给第一组的存储单元，并将第二验证电压分配给存储单元 第二组 以及编程单元，其改变第一组的每个存储单元的阈值电压，直到第一组的每个存储单元的阈值电压大于或等于第一验证电压，并且改变每个存储单元的阈值电压 直到第二组的每个存储单元的阈值电压大于或等于第二验证电压。

    Encoding and/or decoding memory devices and methods thereof
    83.
    发明申请
    Encoding and/or decoding memory devices and methods thereof 有权
    编码和/或解码存储器件及其方法

    公开(公告)号：US20090241009A1

    公开(公告)日：2009-09-24

    申请号：US12232258

    申请日：2008-09-12

    Applicant: Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

    Inventor： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: H03M13/03 ,  G06F11/1072 ,  H03M13/05

    Abstract: Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.

    Abstract translation: 可以提供编码/解码存储器件及其方法。 根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。 处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。 可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。 因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。

    Memory devices and encoding and/or decoding methods
    84.
    发明申请
    Memory devices and encoding and/or decoding methods 有权
    存储器件和编码和/或解码方法

    公开(公告)号：US20090241008A1

    公开(公告)日：2009-09-24

    申请号：US12379746

    申请日：2009-02-27

    Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

    Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

    IPC: H03M13/29 ,  G06F11/10

    CPC classification number: H03M13/2903 ,  G06F11/1072 ,  H03M13/29 ,  H03M13/353

    Abstract: Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.

    Abstract translation: 提供存储器件和/或编码/解码方法。 存储器件可以包括：存储器单元阵列; 内部解码器，被配置为向从存储器单元阵列读取的第一代码字应用基于第一通道的特性选择的第一解码方案，其中读取第一代码字以执行第一代码字的错误控制代码（ECC）解码 代码字，并且应用于从存储单元阵列读取的第二码字，基于第二通道的特性选择的第二解码方案，其中读取第二码字以执行第二码字的ECC解码; 以及外部解码器，被配置为将外部解码方案应用于ECC解码的第一码字和ECC解码的第二码字，以执行第一码字和第二码字的ECC解码。

    Data processing systems and methods providing error correction
    85.
    发明授权
    Data processing systems and methods providing error correction 有权
    提供纠错的数据处理系统和方法

    公开(公告)号：US09100054B2

    公开(公告)日：2015-08-04

    申请号：US13414002

    申请日：2012-03-07

    Applicant: Kijun Lee ,  Junjin Kong ,  Sejin Lim ,  Jaehong Kim ,  Hong-Rak Son ,  Yong-June Kim

    Inventor： Kijun Lee ,  Junjin Kong ,  Sejin Lim ,  Jaehong Kim ,  Hong-Rak Son ,  Yong-June Kim

    IPC: H03M13/29 ,  H03M13/37 ,  H03M13/33 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15

    CPC classification number: H03M13/2906 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2933 ,  H03M13/2957 ,  H03M13/3738

    Abstract: A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.

    Abstract translation: 可以提供一种方法来检测和校正数据系统中的数据错误，其中数据消息已经使用外部奇偶校验比特基于数据消息使用外部编码技术进行编码，以提供外部码字，并且具有基于外部奇偶校验位的内部奇偶校验位 码字使用与外部编码技术不同的内部编码技术来提供内部码字。 该方法可以包括使用内部奇偶校验位和对应于内部编码技术的内部解码技术来执行内部码字的内部解码。 响应于无误地执行内部码字的内部解码，可以从内部码字的内部解码的结果中提取数据消息，而不使用外部奇偶校验位来解码内​​部码字的内部解码结果。 还讨论了相关系统。

    Memory systems and defective block management methods related thereto
    89.
    发明授权
    Memory systems and defective block management methods related thereto 有权
    与其相关的存储器系统和有缺陷的块管理方法

    公开(公告)号：US08417988B2

    公开(公告)日：2013-04-09

    申请号：US12784683

    申请日：2010-05-21

    Applicant: Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

    Inventor： Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

    IPC: G06F11/26 ,  G06F11/00

    CPC classification number: G11C29/82

    Abstract: Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

    Abstract translation: 提供了存储器系统和相关的有缺陷的块管理方法。 用于管理存储器件中的缺陷块的方法包括当存储器块满足缺陷块状态时分配缺陷块。 当分配的缺陷块满足缺陷块取消条件时，分配的缺陷块被取消。

    Nonvolatile memory device using interleaving technology and programming method thereof
    90.
    发明授权
    Nonvolatile memory device using interleaving technology and programming method thereof 有权
    使用交错技术的非易失性存储器件及其编程方法

    公开(公告)号：US08391076B2

    公开(公告)日：2013-03-05

    申请号：US13040626

    申请日：2011-03-04

    Applicant: Hee Seok Eun ,  Yong June Kim

    Inventor： Hee Seok Eun ,  Yong June Kim

    IPC: G11C16/04

    CPC classification number: G11C16/10

    Abstract: A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2N threshold voltage states to N-bit data where N is 2 or a natural number greater than 2, a second controller configured to set a difference between adjacent threshold voltage states among the 2N threshold voltage states so that the difference increases as a threshold voltage increases, and a programming unit configured to form a threshold voltage distribution state corresponding to the allocated threshold voltage state and to program the N-bit data to a multi-level cell. The second controller controls the difference between the adjacent threshold voltage states to equalize the number of read errors for all intersections among the 2N threshold voltage states at the end of life.

    Abstract translation: 提供了一种使用交错技术的非易失性存储器件。 非易失性存储器件包括：第一控制器，被配置为将2N个阈值电压状态中的一个分配给N为2或大于2的自然数的N位数据;第二控制器，被配置为将2N的阈值电压状态之间的差设定为2N 阈值电压状态使得差异随阈值电压增加而增加，并且编程单元被配置为形成与所分配的阈值电压状态相对应的阈值电压分布状态，并将N位数据编程到多电平单元。 第二控制器控制相邻阈值电压状态之间的差异，以平衡在寿命结束时的2N个阈值电压状态之间的所有交点的读取误差的数量。

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