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    Clock and data timing compensation for receiver
    83.
    发明申请
    Clock and data timing compensation for receiver 审中-公开
    接收机的时钟和数据定时补偿

    公开(公告)号：US20060274874A1

    公开(公告)日：2006-12-07

    申请号：US11142764

    申请日：2005-06-01

    Applicant: Arvind Kumar ,  Warren Anderson ,  George Powley ,  Jeff Wight

    Inventor： Arvind Kumar ,  Warren Anderson ,  George Powley ,  Jeff Wight

    IPC: H04L7/04

    CPC classification number: H04L7/033 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0062 ,  H04L7/0334

    Abstract: According to some embodiments, a system provides acquisition of a first sample of a data signal based on a first clock signal associated with a first phase, the first sample associated with a first data eye of a clock cycle, acquisition of a second sample of the data signal based on a second clock signal associated with a second phase, the second sample associated with a second data eye of the clock cycle, determination of whether the first sample reflects expected data associated with the first data eye, control of the first phase of the first clock signal based on whether the first sample reflects the expected data associated with the first data eye, determination of whether the second sample reflects expected data associated with the second data eye, and control of the second phase of the second clock signal based on whether the second sample reflects the expected data associated with the second data eye.

    Abstract translation: 根据一些实施例，系统基于与第一阶段相关联的第一时钟信号提供对数据信号的第一采样的采集，第一采样与时钟周期的第一数据眼相关联，获取第一采样的第一采样 基于与第二阶段相关联的第二时钟信号的数据信号，所述第二样本与所述时钟周期的第二数据眼相关联，确定所述第一样本是否反映与所述第一数据眼相关联的预期数据， 所述第一时钟信号基于所述第一样本是否反映与所述第一数据眼睛相关联的预期数据，确定所述第二样本是否反映与所述第二数据眼睛相关联的预期数据，以及基于所述第二时钟信号的第二相位的控制 第二样本是否反映与第二数据眼睛相关联的预期数据。

    Method and an apparatus for managing power consumption of a server
    85.
    发明申请
    Method and an apparatus for managing power consumption of a server 有权
    用于管理服务器的功耗的方法和装置

    公开(公告)号：US20050283624A1

    公开(公告)日：2005-12-22

    申请号：US10871587

    申请日：2004-06-17

    Applicant: Arvind Kumar ,  David O'Shea

    Inventor： Arvind Kumar ,  David O'Shea

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/171

    Abstract: A method and an apparatus for managing power consumption of a server have been disclosed. In one embodiment, the method includes allowing a user to set a power management policy on a server, monitoring power consumption of a plurality of blades in the server, and automatically managing power consumption of the server in response to the power consumption of the plurality of blades based on the power management policy set by the user. Other embodiments have been claimed and described.

    Abstract translation: 已经公开了一种用于管理服务器的功耗的方法和装置。 在一个实施例中，该方法包括允许用户在服务器上设置电源管理策略，监视服务器中的多个刀片的功耗，以及响应于多个服务器的功耗而自动管理服务器的功耗 基于用户设置的电源管理策略。 已经要求和描述了其它实施例。

    Java common information model interface for windows management instrumentation via COM/DCOM
    87.
    发明授权
    Java common information model interface for windows management instrumentation via COM/DCOM 失效
    Java通用信息模型界面，通过COM / DCOM进行Windows管理

    公开(公告)号：US06854122B1

    公开(公告)日：2005-02-08

    申请号：US09749271

    申请日：2000-12-27

    Applicant: Mohamed S. Sheriff ,  Arvind Kumar

    Inventor： Mohamed S. Sheriff ,  Arvind Kumar

    IPC: G06F9/46 ,  G06F13/00 ,  H04L29/08

    CPC classification number: G06F9/541 ,  H04L67/125

    Abstract: A system and method are disclosed for utilizing a computer with a first operating system to access and perform operations on a second computer having a different operating system, using a web-based adapter routine. A Java console accesses a web based adapter routine to implement a set of Java based APIs to perform CIM operations. The adapter routine, in conjunction with a Java Native Interface and a CIM to WMI mapper enables CIM operations to be performed on a managed server having for example, a Microsoft Operating System or XML based communications.

    Abstract translation: 公开了一种利用具有第一操作系统的计算机利用基于web的适配器例程来访问并且在具有不同操作系统的第二计算机上执行操作的系统和方法。 Java控制台访问基于Web的适配器例程来实现一组基于Java的API来执行CIM操作。 适配器例程与Java本地接口和CIM到WMI映射器相结合，可以在具有Microsoft操作系统或基于XML的通信的受管服务器上执行CIM操作。

    Common source transistor capacitor stack
    88.
    发明授权
    Common source transistor capacitor stack 失效
    共源晶体管电容堆叠

    公开(公告)号：US06337497B1

    公开(公告)日：2002-01-08

    申请号：US08858486

    申请日：1997-05-16

    Applicant: Hussein Ibrahim Hanafi ,  Arvind Kumar ,  Matthew R. Wordeman

    Inventor： Hussein Ibrahim Hanafi ,  Arvind Kumar ,  Matthew R. Wordeman

    IPC: H01L31119

    CPC classification number: H01L27/10808 ,  H01L27/10885

    Abstract: New arrangement of a vertical field effect transistor and a capacitor together forming a memory cell which in turn may be the basic building block of a memory chip, such as a very high density DRAM. The capacitor's first electrode is connected to the drain of the transistor. The transistor's source is connected to the sources of other transistors, the gate is connected to a word line, and the second electrode of said capacitor is connected to a bit line.

    Abstract translation: 垂直场效应晶体管和电容器的新布置一起形成存储器单元，其又可以是存储器芯片的基本构建块，例如非常高密度的DRAM。 电容器的第一电极连接到晶体管的漏极。 晶体管的源极连接到其它晶体管的源极，栅极连接到字线，并且所述电容器的第二电极连接到位线。

    Gated diode structure for eliminating RIE damage from cap removal
    89.
    发明授权
    Gated diode structure for eliminating RIE damage from cap removal 失效
    门二极管结构，用于消除去除盖子的RIE损坏

    公开(公告)号：US08779551B2

    公开(公告)日：2014-07-15

    申请号：US13489537

    申请日：2012-06-06

    Applicant: Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    Inventor： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    IPC: H01L27/06

    CPC classification number: H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

    Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

    Abstract translation: 一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻 其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

    Write-leveling system and method
    90.
    发明授权
    Write-leveling system and method 有权
    写平整系统和方法

    公开(公告)号：US08737161B1

    公开(公告)日：2014-05-27

    申请号：US13769172

    申请日：2013-02-15

    Applicant: Arvind Kumar ,  Shobhit Singhal ,  Vikas Lakhanpal

    Inventor： Arvind Kumar ,  Shobhit Singhal ,  Vikas Lakhanpal

    IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C8/18 ,  G11C5/04 ,  G11C7/1093

    Abstract: A system is provided for use with a DRAM, a DQS signal provider, a clock signal provider, a DQS line and a clock line. The DQS line can provide the DQS signal from the DQS signal provider to the DRAM. The clock line can provide the clock signal from the clock signal provider to the DRAM. The system includes a clock delay determining portion, a DQS delay determining portion, and adjustment portion and a controlling portion. The clock delay determining portion can determine a clock delay. The DQS delay determining portion can determine a DQS delay. The adjustment portion can generate an adjustment value based on the clock delay and the DQS delay. The controlling portion can instruct the DQS signal provider to adjust a time of providing a second DQS signal based on the adjustment value, wherein the clock delay is less than the DQS delay.

    Abstract translation: 提供了一种与DRAM，DQS信号提供器，时钟信号提供器，DQS线和时钟线一起使用的系统。 DQS线路可以将来自DQS信号提供器的DQS信号提供给DRAM。 时钟线可以将来自时钟信号提供器的时钟信号提供给DRAM。 该系统包括时钟延迟确定部分，DQS延迟确定部分和调整部分以及​​控制部分。 时钟延迟确定部分可以确定时钟延迟。 DQS延迟确定部分可以确定DQS延迟。 调整部分可以基于时钟延迟和DQS延迟生成调整值。 控制部分可以指示DQS信号提供者基于调整值来调整提供第二DQS信号的时间，其中时钟延迟小于DQS延迟。

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