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172 条记录 (耗时 0.027 秒)

    Flash memory cell, flash memory device and manufacturing method thereof
    81.
    发明授权
    Flash memory cell, flash memory device and manufacturing method thereof 有权
    闪存单元，闪存设备及其制造方法

    公开(公告)号：US07087950B2

    公开(公告)日：2006-08-08

    申请号：US10835390

    申请日：2004-04-30

    申请人： Josef Willer ,  Frank Lau

    发明人： Josef Willer ,  Frank Lau

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78645

    摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

    摘要翻译： 本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状 包围所述有源区域的所述突出部分。 本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

    Method for producing semiconductor memory devices and integrated memory device
    82.
    发明申请
    Method for producing semiconductor memory devices and integrated memory device 有权
    用于制造半导体存储器件和集成存储器件的方法

    公开(公告)号：US20060145227A1

    公开(公告)日：2006-07-06

    申请号：US11371743

    申请日：2006-03-09

    申请人： Josef Willer

    发明人： Josef Willer

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

    摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

    摘要翻译： 本发明提供了一种用于存储单元阵列，特别是电荷捕获存储单元阵列的集成方案，其包括局部互连的架构，其能够避免字线堆叠的氮化物绝缘并且在标准技术中产生不同结构和尺寸的CMOS器件 以及更高级的存储单元晶体管。

    Non-volatile semiconductor memory device
    83.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07061046B2

    公开(公告)日：2006-06-13

    申请号：US10952233

    申请日：2004-09-28

    申请人： Josef Willer ,  Thomas Mikolajick

    发明人： Josef Willer ,  Thomas Mikolajick

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/792

    摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.

    摘要翻译： 位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。 至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。 存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。 它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

    Charge-trapping memory device and methods for operating and manufacturing the cell
    85.
    发明申请
    Charge-trapping memory device and methods for operating and manufacturing the cell 有权
    电荷捕获存储器件以及用于操作和制造电池的方法

    公开(公告)号：US20060091448A1

    公开(公告)日：2006-05-04

    申请号：US11253939

    申请日：2005-10-19

    申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

    摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

    摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    86.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
    非易失性半导体存储器件

    公开(公告)号：US20060065921A1

    公开(公告)日：2006-03-30

    申请号：US10952233

    申请日：2004-09-28

    申请人： Josef Willer ,  Thomas Mikolajick

    发明人： Josef Willer ,  Thomas Mikolajick

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/792

    摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.

    摘要翻译： 位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。 至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。 存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。 它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

    Semiconductor memory having charge trapping memory cells and fabrication method
    87.
    发明申请
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US20050286296A1

    公开(公告)日：2005-12-29

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    Memory cell array comprising individually addressable memory cells and method of making the same
    89.
    发明授权
    Memory cell array comprising individually addressable memory cells and method of making the same 有权
    包含单独可寻址存储单元的存储单元阵列及其制造方法

    公开(公告)号：US06888753B2

    公开(公告)日：2005-05-03

    申请号：US10680383

    申请日：2003-10-06

    申请人： Ronald Kakoschke ,  Josef Willer

    发明人： Ronald Kakoschke ,  Josef Willer

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  G11C11/34

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203

    摘要： A memory cell array comprises a plurality of memory transistors arranged in a two-dimensional array, each memory transistor having two source/drain regions arranged in a first direction of the memory cell array with a channel substrate region therebetween, and a gate structure arranged above the channel substrate region. The source/drain regions and channel substrate regions are formed in a substrate arranged on an insulating layer, with the channel substrate regions of memory transistors adjacent each other in the first direction being separated from each other by respective source/drain regions extending down to the insulating layer. The source/drain regions and the channel substrate regions of memory transistors adjacent each other in a second direction of the memory cell array furthermore are isolated from each other by trenches filled with insulating material and formed in the substrate so as to extend down to the insulating layer.

    摘要翻译： 存储单元阵列包括以二维阵列排列的多个存储晶体管，每个存储晶体管具有沿存储单元阵列的第一方向布置的两个源极/漏极区域，其间具有沟道衬底区域，并且栅极结构布置在 沟道衬底区域。 源极/漏极区域和沟道衬底区域形成在布置在绝缘层上的衬底中，其中在第一方向上彼此相邻的存储晶体管的沟道衬底区域通过相应的源极/漏极区域彼此分开， 绝缘层。 在存储单元阵列的第二方向上彼此相邻的存储晶体管的源极/漏极区域和沟道衬底区域进一步由填充有绝缘材料的沟槽彼此隔离，并形成在衬底中，以向下延伸到绝缘 层。

    Charge trapping memory cell
    90.
    发明申请
    Charge trapping memory cell 有权
    电荷捕获存储单元

    公开(公告)号：US20050045963A1

    公开(公告)日：2005-03-03

    申请号：US10894348

    申请日：2004-07-19

    申请人： Frank Lau ,  Josef Willer

    发明人： Frank Lau ,  Josef Willer

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792 ,  G11C11/34

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

    摘要： A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

    摘要翻译： 存储单元包括在半导体本体的顶侧的源/漏区之间的沟道区，并且相对于纵向方向横向地设置有形成在半导体材料中的凸起。 这导致径向电场的强度的均匀分布，并且避免了在通道区​​域的横向边缘处的场强尖峰。 存储层序列位于通道区域和栅电极之间，作为字线的一部分。