公开(公告)号：US06235599B1

公开(公告)日：2001-05-22

申请号：US09426402

申请日：1999-10-25

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L29/6659

Abstract: A shallow doped junction that is part of an integrated circuit device within a semiconductor substrate is formed with box-shaped implant profiles for implantation of the amorphizing implant species and the dopant implant species such that the doped junction has minimized sheet resistance. A box-shaped implant profile for implantation of the amorphizing implant species is formed from implantation of the amorphizing implant species with a plurality of projection ranges to form a plurality of implant profiles. A box-shaped implant profile for implantation of the dopant implant species is formed from implantation of the dopant implant species with a plurality of projection ranges to form a plurality of implant profiles. In addition, each of the plurality of implant profiles for the dopant implant species is preferably below the solid solubility of the dopant implant species within the semiconductor substrate. By controlling the implant profiles of the amorphizing implant species and the dopant implant species during fabrication of the doped junction, the sheet resistance of the doped junction is minimized. In addition, the temperature and the time period for activating the dopant implant species in a RTA (Rapid Thermal Anneal) process is also minimized such that the doped junction remains relatively shallow.

Abstract translation: 作为半导体衬底内的集成电路器件的一部分的浅掺杂结形成有用于注入非晶化注入物种和掺杂剂注入物种的盒形注入轮廓，使得掺杂结具有最小的薄层电阻。 用于植入非晶化植入物种的盒形植入物轮廓通过用多个投影范围的植入非晶化植入物种形成，以形成多个植入物轮廓。 通过用多个投影范围注入掺杂剂注入物种来形成用于注入掺杂剂注入种类的盒状植入物轮廓，以形成多个植入物轮廓。 此外，用于掺杂剂注入物种的多个植入物轮廓中的每一个优选低于半导体衬底内的掺杂剂注入种类的固体溶解度。 通过在掺杂结的制造过程中控制非晶化注入物种和掺杂剂注入物种的种植体轮廓，掺杂结的薄层电阻最小化。 此外，在RTA（快速热退火）工艺中激活掺杂剂注入物质的温度和时间段也被最小化，使得掺杂的结保持相对较浅。

公开(公告)号：US06225661B1

公开(公告)日：2001-05-01

申请号：US09145786

申请日：1998-09-02

Applicant: Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

Inventor： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC: H01L27088

CPC classification number: H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract translation: 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06225173B1

公开(公告)日：2001-05-01

申请号：US09187172

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66621 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method of fabricating an integrated circuit with ultra-shallow source and drain junctions utilizes a damascene process. The substrate is over-etched to form extensions in the source and drain regions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极和漏极结的集成电路的方法利用镶嵌工艺。 衬底被过蚀刻以在源区和漏区中形成延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06221724B1

公开(公告)日：2001-04-24

申请号：US09187252

申请日：1998-11-06

Applicant: Bin Yu ,  Shekhar Pramanick

Inventor： Bin Yu ,  Shekhar Pramanick

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26533 ,  H01L21/2658 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1083

Abstract: An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention utilizes an inert ion implantation process whereby inert ions are implanted through a fabricated gate structure on the semiconductor substrate to form a region of inert ion implant between source and drain regions of a device on the integrated circuit. This accumulation region prevents punch-through between source and drain regions of the device. In a second embodiment, the inert ion implantation is used in conjunction with the conventional punch-through dopant implant. In this second embodiment, diffusion of the implant during subsequent thermal annealing is suppressed by the inert ion accumulation in the subsurface region of the device. Accordingly, improved integrated circuits and methods of fabricating an integrated circuit having punch-through suppression are disclosed.

Abstract translation: 为具有穿通抑制的集成电路提供集成电路和制造方法。 不同于常规的穿透抑制方法，其中在器件中制造掺杂剂注入，本发明利用惰性离子注入工艺，其中惰性离子通过半导体衬底上制造的栅极结构注入，以形成惰性离子注入区域 集成电路上的器件的源极和漏极区域。 该积聚区域防止器件的源极和漏极区域之间穿透。 在第二实施例中，惰性离子注入与常规穿通掺杂剂注入相结合使用。 在该第二实施例中，通过装置的地下区域中的惰性离子累积来抑制随后的热退火期间的植入物的扩散。 因此，公开了改进的集成电路和制造具有穿通抑制的集成电路的方法。

公开(公告)号：US06214681B1

公开(公告)日：2001-04-10

申请号：US09491843

申请日：2000-01-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/82345 ,  H01L29/49 ,  Y10S148/058

Abstract: An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs utilize gate structures with heavily doped polysilicon and germanium material. The polysilicon and germanium materials or thin films are manufactured by low pressure chemical vapor deposition. A silicon buffer layer and oxide cap is used to prevent germanium outgassing.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET利用具有重掺杂多晶硅和锗材料的栅极结构。 多晶硅和锗材料或薄膜通过低压化学气相沉积制造。 硅缓冲层和氧化物盖用于防止锗脱气。

公开(公告)号：US06213869B1

公开(公告)日：2001-04-10

申请号：US09309105

申请日：1999-05-10

Applicant: Bin Yu ,  John C. Holst

Inventor： Bin Yu ,  John C. Holst

IPC: H01L218249

CPC classification number: H01L29/78615 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/1079 ,  H01L29/78 ,  H01L29/7841

Abstract: A coupling capacitor is coupled between the gate and the body region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The body region of the MOSFET is electrically isolated to form a floating body region. The capacitance of the coupling capacitor is designed such that a BJT (Bipolar Junction Transistor) connected in parallel with the MOSFET turns on when the MOSFET turns on. In addition such a design of the coupling capacitor lowers the magnitude of the threshold voltage of the MOSFET when the MOSFET is turned on. Furthermore, the capacitance of the coupling capacitor is designed such that the magnitude of the threshold voltage of the MOSFET is raised when the MOSFET is turned off. Thus, the MOSFET type device of the present invention has both higher drive current when the MOSFET is turned on and lower steady state power dissipation when the MOSFET is turned off with a variable threshold voltage.

Abstract translation: 耦合电容器耦合在MOSFET（金属氧化物半导体场效应晶体管）的栅极和体区之间。 MOSFET的体区电气隔离以形成浮体区域。 耦合电容器的电容设计成使得当MOSFET导通时，与MOSFET并联连接的BJT（双极结晶体管）导通。 此外，当MOSFET导通时，耦合电容的这种设计降低了MOSFET的阈值电压的幅度。 此外，耦合电容器的电容被设计成使得当MOSFET被断开时MOSFET的阈值电压的幅度上升。 因此，本发明的MOSFET型器件在MOSFET导通时具有较高的驱动电流，并且当MOSFET以可变阈值电压关断时具有较低的稳态功耗。

公开(公告)号：US06190952B1

公开(公告)日：2001-02-20

申请号：US09261273

申请日：1999-03-03

Applicant: Qi Xiang ,  Bin Yu

Inventor： Qi Xiang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs are provided on an SOI substrate. The thickness of a thin film on the substrate is varied to adjust the threshold voltage. The threshold voltage can be varied by roughly 240 mV. The thickness of the thin film can be adjusted through a LOCOS process.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET设置在SOI衬底上。 改变衬底上薄膜的厚度以调节阈值电压。 阈值电压可以改变大约240 mV。 薄膜的厚度可以通过LOCOS工艺进行调整。

公开(公告)号：US06184097B2

公开(公告)日：2001-02-06

申请号：US09255604

申请日：1999-02-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492

Abstract: A method of fabricating an integrated circuit with ultra-shallow source and drain junctions utilizes a dummy or sacrificial gate spacer. Ions are implanted and dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with an insulative layer. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极和漏极结的集成电路的方法利用虚拟或牺牲栅极间隔物。 植入离子并且通过与牺牲隔离物相关联的开口提供掺杂剂以形成源极和漏极延伸部。 开口可以填充绝缘层。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFETS）。

公开(公告)号：US6107667A

公开(公告)日：2000-08-22

申请号：US151146

申请日：1998-09-10

Applicant: Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

Inventor： Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L27/088 ,  H01L27/095 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L21/28194 ,  H01L21/28123 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/90

Abstract: A method for making a ULSI MOSFET includes establishing a void in a field oxide layer on a silicon substrate and filling the center of the void with a gate electrode. A high-k gate insulator is sandwiched between the gate electrode and the substrate. Around the void, a low-k gate spacer is formed, with the gate spacer being disposed directly above the source and drain extensions of the MOSFET.

Abstract translation: 制造ULSI MOSFET的方法包括在硅衬底上的场氧化物层中建立空隙并用栅电极填充空隙的中心。 高k栅极绝缘体夹在栅电极和衬底之间。 围绕空隙，形成低k栅极间隔物，栅极间隔物直接设置在MOSFET的源极和漏极延伸部分的上方。

公开(公告)号：US6051470A

公开(公告)日：2000-04-18

申请号：US231651

申请日：1999-01-15

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/66545

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract translation: 具有减少的热载流子注入和穿通的半导体器件由双栅极电极形成，该双栅电极包括边缘导电部分，中心导电部分和形成在边缘导电部分和中心导电部分之间的电介质侧壁间隔物。 边缘导电部分提供抵抗有源区域的高电势势垒，从而降低阈值电压滚降和漏电流。