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210 条记录 (耗时 0.026 秒)

    Programming mode selection with JTAG circuits
    81.
    发明授权
    Programming mode selection with JTAG circuits 失效
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06421812B1

    公开(公告)日：2002-07-16

    申请号：US09094186

    申请日：1998-06-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    DQS postamble filtering
    82.
    发明授权
    DQS postamble filtering 有权
    DQS后同步码过滤

    公开(公告)号：US07324405B1

    公开(公告)日：2008-01-29

    申请号：US11368369

    申请日：2006-03-03

    申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    IPC分类号： G11C8/00

    CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

    摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

    摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
    83.
    发明授权
    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device 有权
    LVDS接口结合了可编程逻辑器件中的锁相环电路

    公开(公告)号：US06373278B1

    公开(公告)日：2002-04-16

    申请号：US09758674

    申请日：2001-01-11

    申请人： Chiakang Sung ,  Bonnie I. Wang ,  Richard G. Cliff

    发明人： Chiakang Sung ,  Bonnie I. Wang ,  Richard G. Cliff

    IPC分类号： H03K19173

    CPC分类号： H03L7/18 ,  H03L7/07 ,  H03L7/0891

    摘要： An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.

    摘要翻译： 用于可编程逻辑器件的LVDS接口使用锁相环（“PLL”）电路为数据输入和输出提供数据时钟。 PLL时钟是高精度的，每个包括一个乘以W的计数器，以便可以使用倍增和非乘法时钟。 倍增时钟用于将数据串行时移到或移出移位寄存器链。 非乘法时钟用于并行加载或读取移位寄存器链中的寄存器。 从单个PLL提供相乘和非乘法时钟确保时钟处于正确的相位关系，以便串行输入或输出以及并行加载或卸载被正确同步。

    MULTIPLE DATA RATE INTERFACE ARCHITECTURE
    85.
    发明申请
    MULTIPLE DATA RATE INTERFACE ARCHITECTURE 有权
    多种数据速率接口架构

    公开(公告)号：US20120146700A1

    公开(公告)日：2012-06-14

    申请号：US13324354

    申请日：2011-12-13

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H03K5/06

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
    86.
    发明申请
    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES 有权
    可编程逻辑器件中的写层次实现

    公开(公告)号：US20080201597A1

    公开(公告)日：2008-08-21

    申请号：US11843123

    申请日：2007-08-22

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    IPC分类号： G06F1/12 ,  H04L7/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices
    87.
    发明授权
    Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices 有权
    用于在可编程逻辑器件中提供高效和区域有效的去耦电容的装置和方法

    公开(公告)号：US07309906B1

    公开(公告)日：2007-12-18

    申请号：US11097503

    申请日：2005-04-01

    申请人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

    发明人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

    IPC分类号： H01L29/00 ,  H01L21/8242

    CPC分类号： H01L29/94 ,  H01L27/0203

    摘要： Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.

    摘要翻译： 提供了改进的去耦电容器设计和布局方案，其在比先前已知的去耦电容器设计更高的频率下产生高有效电容和高的面积效率。 改进的去耦电容器设计利用具有较短沟道长度的晶体管栅极来减小沟道的总寄生电阻，从而在较高频率下提供更高的有效电容。 为了实现该去耦电容器设计的更高的面积效率，多余的触点被以栅格或华夫饼形式的多晶硅替代。

    Phase-locked loop circuitry for programmable logic devices
    88.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US07190755B1

    公开(公告)日：2007-03-13

    申请号：US10266092

    申请日：2002-10-04

    申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I Wang ,  Richard G Cliff

    发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I Wang ,  Richard G Cliff

    IPC分类号： H03D3/24

    CPC分类号： H03K19/1774 ,  H03K19/177 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/183

    摘要： A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.

    摘要翻译： 锁相环电路（“PLL”）可在相位和频率两个方面调节。 通过在PLL的压控振荡器上提供多个抽头，并提供单独的多路复用器，每个复用器可以为PLL反馈回路选择不同的抽头，并为PLL输出选择一个，一个允许用户调整 输出的相位相对于输入的相位。 类似地，通过提供可加载的预缩放（除以N），后标尺（除以K）和反馈量表（除以M）计数器，允许用户将输出的频率调整为M /（NK ）倍的输入。

    Multiple data rate interface architecture
    89.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US07167023B1

    公开(公告)日：2007-01-23

    申请号：US11059299

    申请日：2005-02-15

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    Multiple data rate interface architecture
    90.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US06806733B1

    公开(公告)日：2004-10-19

    申请号：US10038737

    申请日：2002-01-02

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。