公开(公告)号：US06309928B1

公开(公告)日：2001-10-30

申请号：US09208913

申请日：1998-12-10

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

摘要翻译： 公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。 在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。 这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。 由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。 因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

公开(公告)号：US06277686B1

公开(公告)日：2001-08-21

申请号：US09347546

申请日：1999-07-06

申请人： Chung-Ker Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Chung-Ker Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L218242

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11531

摘要： A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

公开(公告)号：US06242308B1

公开(公告)日：2001-06-05

申请号：US09354671

申请日：1999-07-16

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

IPC分类号： H01L218247

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in forming the floating gate, and also using to advantage a so-called “smiling effect” which is normally taught away. The smiling effect, or an uneven thickening of an oxide layer, comes into play while growing interpoly oxide where concurrently the oxidation of the polysilicon gate advances in such a manner so as to form a sharp and reliable poly tip. The invention is also directed to providing a split gate flash memory cell having a thin floating gate and a poly tip therein.

摘要翻译： 公开了一种用于形成具有薄浮动栅极和尖锐多晶硅尖端的分裂栅极快闪存储器单元的方法，以便提高电池的擦除和编程速度。 该方法包括使用通常用于形成浮动栅极的多晶氧化物以外的氧化物，并且还利用通常被教导的所谓的“微笑效果”。 微生物效应或氧化物层的不均匀增厚在生长多晶氧化物的同时发生，同时多晶硅栅极的氧化同时进行以形成尖锐且可靠的多晶硅尖端。 本发明还涉及提供一种具有薄的浮动栅极和多个尖端的分裂栅极闪存单元。

公开(公告)号：US06229176B1

公开(公告)日：2001-05-08

申请号：US09257833

申请日：1999-02-25

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

摘要翻译： 提供了一种用于形成分支栅极快闪存储器单元的方法，其具有支撑不同厚度的多晶硅氧化物的台阶聚合物，以改善电池的全部性能。 多晶氧化物形成在第一多晶硅层的部分上，该第一多晶硅层又被部分蚀刻以形成邻近聚氧化物下面的浮动栅极的侧壁的台阶。 接着在步骤poly上由热的温度氧化物形成间隔物。 然后形成间极氧氮化物，并且控制栅极被图案化与浮置栅极与介入的多晶硅氧化物重叠。 步进多晶硅和间隔件在控制栅极和浮动栅极之间形成适当的距离，同时保持多晶硅尖端和控制栅极之间的距离不变，使得控制栅极和浮动栅极之间以及浮动栅极和浮动栅极之间的适当耦合 实现了衬底，从而改进了具有阶梯聚光的分离栅极闪存的全部性能。

公开(公告)号：US06228695B1

公开(公告)日：2001-05-08

申请号：US09320759

申请日：1999-05-27

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by depositing a poly-2 layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate flash memory cell.

摘要翻译： 公开了一种具有自对准源和对准控制栅极的浮置栅极的分裂栅极闪存单元及其形成方法。 这通过在硅衬底上的栅极氧化物层上沉积多晶层来实现，以形成垂直控制栅极，随后沉积多晶硅层以形成与控制栅极相邻的间隔物浮动栅极，其中间隔栅极氧化层 。 源极是自对准的，并且浮栅也形成为与对栅极自对准，从而可以减小电池的尺寸。 所产生的自对准源减轻了从源极到控制栅极的穿通，而相对于控制栅极的自对准浮动栅极提供了改进的可编程性。 该方法也取代了传统的多晶氧化工艺，从而产生改善的浮栅的尖峰，以改善分离栅闪存单元的擦除和写入。

公开(公告)号：US06180977B2

公开(公告)日：2001-01-30

申请号：US09389631

申请日：1999-09-03

申请人： Yai-Fen Lin ,  Hung-Cheng Sung ,  Chia-Ta Hsieh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Hung-Cheng Sung ,  Chia-Ta Hsieh ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions in said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.

摘要翻译： 提供了一种用于制造自对准边缘注入分裂栅极闪存的方法，该闪存包括形成有分离的第二和第二区域的第一导电类型的半导体衬底，第一和第二区域限定衬底沟道区域 之间; 通过氧化物层与衬底中的掺杂区域分离的浮置栅极; 由所述浮动栅极部分地由绝缘体覆盖并分离的控制栅极; 所述浮栅具有薄部分和厚部分; 并且所述浮动栅极的所述薄部分覆盖所述半导体衬底中的两个掺杂区域，以减少表面泄漏电流并提高存储器单元的编程速度。

公开(公告)号：US6159801A

公开(公告)日：2000-12-12

申请号：US298932

申请日：1999-04-26

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

公开(公告)号：US6121088A

公开(公告)日：2000-09-19

申请号：US156054

申请日：1998-09-17

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-ke Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/4763

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： Form a split gate EEPROM memory device on a doped silicon semiconductor substrate starting with an initial oxide layer and form an undoped first polysilicon layer thereon. Then form a polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.

摘要翻译： 在掺杂硅半导体衬底上形成一个分裂栅极EEPROM存储器件，从初始氧化层开始并在其上形成未掺杂的第一多晶硅层。 然后在未掺杂的第一多晶硅层上形成多晶硅氧化物硬掩模，用于图案化初始氧化物层和未掺杂的第一多晶硅层，然后将其从未掺杂的第一多晶硅层和初始氧化物层上蚀刻形成浮栅电极堆叠 底物。 然后形成隧道氧化物层和掺杂多晶硅并将它们图案化成控制栅极电极堆叠，其中控制栅极电极堆叠相对于浮动栅电极堆叠位于分离栅极配置中。

公开(公告)号：US06093607A

公开(公告)日：2000-07-25

申请号：US4806

申请日：1998-01-09

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hong-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hong-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory. This is accomplished in two embodiments where in the first, fluorine is implanted in the first polysilicon layer to form the floating gate. It is disclosed here that the implanting of fluorine increases the oxidation rate of the polysilicon and because of the faster oxidation, the polygate bird's beak (GBB) that is formed attains a relatively short and sharp shape in comparison with conventional beaks. This has the attendant benefit of forming a relatively small memory cell, and the concomitant increase in the erase speed of the cell. In the second embodiment, oxygen is used with the same favorable results. A third embodiment discloses the structure of a split-gate flash memory cell having a sharp bird's beak.

摘要翻译： 提供了一种用于形成短而尖锐的门鸟喙的方法，以便增加分闸门闪存的擦除速度。 这在两个实施方案中实现，其中在第一个中，将氟注入第一多晶硅层以形成浮栅。 这里公开的是，氟的注入增加了多晶硅的氧化速率，并且由于更快的氧化，与常规的喙相比，形成的多孔鸟喙（GBB）具有相对较短且锐利的形状。 这具有形成相对小的存储单元的伴随的益处，并且伴随着单元的擦除速度的增加。 在第二实施例中，使用氧气具有相同的有利结果。 第三实施例公开了具有尖锐鸟喙的分裂式闪存单元的结构。

公开(公告)号：US6005809A

公开(公告)日：1999-12-21

申请号：US100815

申请日：1998-06-19

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/02

CPC分类号： G11C16/10 ,  G11C16/0425 ,  G11C16/14

摘要： A method to program data to and erase data from a split gate flash EEPROM to improve programming and erasing speed, and to improve endurance is disclosed. The programming the split gate flash EEPROM cell is accomplished by simultaneously applying a first positive voltage to the control gate, applying a first moderately negative voltage to the semiconductor substrate, applying a slight potential to the drain region to supply a constant programming current, and applying a second positive voltage to the drain region. The first positive voltage, the first moderately negative voltage, the slight positive potential and the second positive voltage are applied for a sufficient time to cause electrons to be trapped on the floating gate. The erasing of the split gate flash EEPROM cell is accomplished by simultaneously applying a large positive voltage to the control gate, applying the first moderately negative voltage to the semiconductor substrate, applying a second moderately negative voltage to the source region, and applying the ground reference potential or floating the drain region. The large positive voltage, the first moderately negative voltage, and the second moderately negative voltage is applied for a sufficient time period to institute Fowler-Nordheim tunneling from the floating gate to the control gate to eliminate any electrons from the floating gate.

摘要翻译： 公开了一种用于将数据编程到数据并从其中擦除数据的方法，以提高编程和擦除速度，并提高耐久性。 分裂栅极快闪EEPROM单元的编程通过同时向控制栅极施加第一正电压，向半导体衬底施加第一中等负电压，向漏区施加微小电位以提供恒定的编程电流并施加 向漏极区域施加第二正电压。 施加第一正电压，第一中等负电压，轻微正电位和第二正电压足够的时间以使电子被捕获在浮栅上。 分裂栅极快闪EEPROM单元的擦除是通过同时向控制栅极施加大的正电压，向半导体衬底施加第一中等负电压，向源极区施加第二适度负电压，以及施加接地参考 电位或浮置漏极区。 施加大的正电压，第一中等负电压和第二适中负电压足够的时间段，以将Fowler-Nordheim隧道从浮栅施加到控制栅极，以从浮栅去除任何电子。