公开(公告)号：US20050285222A1

公开(公告)日：2005-12-29

申请号：US11137075

申请日：2005-05-25

申请人： Kong-Beng Thei ,  Chung Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L23/525 ,  H01L23/532 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US08981562B2

公开(公告)日：2015-03-17

申请号：US12134381

申请日：2008-06-06

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

IPC分类号： H01L21/00 ,  G03F1/00 ,  G03F1/36 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/481 ,  G03F1/144 ,  G03F1/36 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

摘要翻译： 提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。 用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。 该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。 如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。 然后形成照相掩模。 可以使用光掩膜形成半导体结构。

公开(公告)号：US08735235B2

公开(公告)日：2014-05-27

申请号：US12276015

申请日：2008-11-21

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Ming-Yuan Wu ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Ming-Yuan Wu ,  Mong-Song Liang

IPC分类号： H01L21/338

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833

摘要： A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

摘要翻译： 提供一种使用门最后工艺形成金属栅的方法。 在基板上形成沟槽。 沟槽的轮廓被修改以在沟槽的孔处提供第一宽度，并且在沟槽的底部提供第二宽度。 轮廓可以通过包括锥形侧壁形成。 金属栅极可以形成在具有改变的轮廓的沟槽中。 还提供了一种半导体器件，其包括在栅极顶部具有比栅极的底部更大的宽度的栅极结构。

公开(公告)号：US08624295B2

公开(公告)日：2014-01-07

申请号：US12052389

申请日：2008-03-20

申请人： Harry Chuang ,  Hung-Chih Tsai ,  Kong-Beng Thei ,  Mong-Song Liang

发明人： Harry Chuang ,  Hung-Chih Tsai ,  Kong-Beng Thei ,  Mong-Song Liang

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L27/092

CPC分类号： H01L21/8238 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104

摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

摘要翻译： 提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。 绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。 绝缘层基本上从半导体衬底表面升高。 升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。 形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。

公开(公告)号：US08558278B2

公开(公告)日：2013-10-15

申请号：US11849798

申请日：2007-09-04

申请人： Harry Chuang ,  Kong-Beng Thei ,  Wen-Huei Guo ,  Mong Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Wen-Huei Guo ,  Mong Song Liang

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.

摘要翻译： 应变感应层形成在MOS器件的顶部，以增加沟道区中的载流子迁移率。 在优选实施例中，应变诱导层的尺寸可导致优化的驱动电流增加和改进的NMOS和PMOS器件中的驱动电流均匀性。 优选实施例的优点是在不添加复杂的处理步骤的情况下获得改进的设备性能。 优选实施例的另一个优点是附加的处理步骤可以容易地集成到已知的CMOS工艺流程中。 此外，创建定义拉伸和压缩应变诱导层的光罩不需要对现有设计数据库进行额外的设计工作。

公开(公告)号：US08368136B2

公开(公告)日：2013-02-05

申请号：US12256132

申请日：2008-10-22

申请人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

发明人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

IPC分类号： H01L27/04

CPC分类号： H01L27/0629 ,  H01L27/11 ,  H01L29/94

摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.

摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。 所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料 电极。

公开(公告)号：US08349680B2

公开(公告)日：2013-01-08

申请号：US12536629

申请日：2009-08-06

申请人： Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Yu Chao Lin

发明人： Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Yu Chao Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/31645 ,  H01L21/31604 ,  H01L21/823842

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层 第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分 并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

公开(公告)号：US08216888B2

公开(公告)日：2012-07-10

申请号：US13079435

申请日：2011-04-04

申请人： Harry Chuang ,  Kong-Beng Thei

发明人： Harry Chuang ,  Kong-Beng Thei

IPC分类号： H01L21/82

CPC分类号： H01L29/4238 ,  H01L21/823437 ,  H01L27/0207

摘要： A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening.

摘要翻译： 形成集成电路结构的方法包括提供包括第一有源区和第二有源区的衬底; 在所述衬底上形成栅电极层; 并蚀刻栅电极层。 栅极电极层的其余部分包括彼此基本平行的第一栅极条和第二栅极条; 以及不平行于并互连第一栅极条和第二栅极条的牺牲条。 牺牲条在第一有源区和第二有源区之间。 所述方法还包括形成覆盖所述第一栅极条和所述第二栅极条的部分的掩模层，其中所述牺牲条和所述第一栅极条和所述第二栅极条的部分通过所述掩模层中的开口暴露; 并且蚀刻所述牺牲条和所述第一栅极条和所述第二栅极条的所述部分通过所述开口。

公开(公告)号：US20120012948A1

公开(公告)日：2012-01-19

申请号：US13245494

申请日：2011-09-26

申请人： Ching-Han Yeh ,  Chen-Pin Hsu ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang

发明人： Ching-Han Yeh ,  Chen-Pin Hsu ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的源极和漏极区域以及设置在源极和漏极区域之间的衬底上的栅极结构。 栅极结构包括在衬底上形成的界面层，在界面层上形成的高k电介质，以及形成在包括第一金属层和第二金属层的高k电介质上的金属栅，其中第一金属 层形成在栅极结构的侧壁的一部分上，并且第二金属层形成在栅极结构的侧壁的另一部分上。

公开(公告)号：US20110284972A1

公开(公告)日：2011-11-24

申请号：US13204461

申请日：2011-08-05

申请人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

发明人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

摘要翻译： 提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在 源极/漏极区域。 上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。