公开(公告)号：US20050127464A1

公开(公告)日：2005-06-16

申请号：US10731503

申请日：2003-12-10

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/329 ,  H01L27/08 ,  H01L29/06 ,  H01L29/872 ,  H01L21/338 ,  H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC classification number: H01L29/66143 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/872

Abstract: A power Schottky rectifier device having pluralities of trenches are disclosed. The Schottky barrier rectifier device includes field oxide region having p-doped region formed thereunder to avoid premature of breakdown voltage and having a plurality of trenches formed in between field oxide regions to increase the anode area thereto increase forward current capacity or to shrinkage the planar area for driving the same current capacity. Furthermore, the trenches have rounded corners to alleviate current leakage and LOCOS region in the active region to relief stress during the bonding process. The processes for power Schottky barrier rectifier device including termination region formation need only three masks and thus can gain the benefits of cost down.

Abstract translation: 公开了具有多个沟槽的功率肖特基整流器件。 肖特基势垒整流装置包括具有形成在其下面的p掺杂区域的场氧化物区域，以避免击穿电压过早，并且在场氧化物区域之间形成多个沟槽，以增加阳极面积，从而增加正向电流容量或缩小平面面积 用于驱动相同的当前容量。 此外，沟槽具有圆角以减轻有源区域中的电流泄漏和LOCOS区域，以在接合过程中释放应力。 包括终端区域形成的功率肖特基势垒整流器装置的处理只需要三个掩模，从而可以获得降低成本的好处。

公开(公告)号：US06649308B1

公开(公告)日：2003-11-18

申请号：US09050670

申请日：1998-03-30

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: G03F900

CPC classification number: H01L29/6653 ,  H01L21/2236 ,  H01L21/2255 ,  H01L21/2652 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are formed in the substrate. A metal silicide contact is formed on the top surface of the gate structure, and on the surface of the source and drain regions. Extended source and drain regions are formed beneath the side-wall spacers and connect next to the source and drain regions.

Abstract translation: 半导体衬底中的超短沟道晶体管包括形成在衬底上的栅极结构。 在门结构的侧壁上形成侧壁间隔物作为杂质扩散源。 源极和漏极区域形成在衬底中。 在栅极结构的顶表面上和源极和漏极区域的表面上形成金属硅化物接触。 扩展的源极和漏极区域形成在侧壁间隔物的下方，并在源极和漏极区域旁边连接。

公开(公告)号：US06555438B1

公开(公告)日：2003-04-29

申请号：US09275134

申请日：1999-03-23

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21336

CPC classification number: H01L29/7834 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S977/779

Abstract: A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is formed on the substrate and on sidewalls of the first conductive layer. The first dielectric layer is removed. Extended source and drain junctions are formed in the substrate under a region covered by the first thermal oxide layer. Sidewall spacers are formed on the sidewalls of the gate structure to protect the extended source and drain junctions therebeneath from being silicided. The second thermal oxide layer is removed to form recessed regions on a substrate surface. A first metal layer is formed on the substrate after the first dielectric layer is removed. Source/drain regions under the recessed regions are formed.

Abstract translation: 描述了一种用于制造具有凹陷的自对准硅化物接触和扩展的源极/漏极结的MOSFET的方法。 在基板上形成具有栅极绝缘层，第一导电层和第一介电层的栅极结构。 在基板上和第一导电层的侧壁上形成热氧化层。 去除第一介电层。 在由第一热氧化物层覆盖的区域下的衬底中形成扩展源极和漏极结。 侧壁间隔件形成在栅极结构的侧壁上，以保护其下方的延伸源极和漏极结不被硅化。 去除第二热氧化物层以在衬底表面上形成凹陷区域。 在去除第一介电层之后，在基板上形成第一金属层。 形成凹陷区域下方的源极/漏极区域。

公开(公告)号：US06548362B1

公开(公告)日：2003-04-15

申请号：US09325811

申请日：1999-06-04

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659

Abstract: A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations. Then, a polysilicon layer and an oxide layer are deposited in order on all areas. Subsequently, an etched-back using the nitride layer a stopping layer is achieved. After that the nitride layer is removed thereby, forming a gate hollow region. After the pad oxide layer is removed, an oxynitride layer is regrown to be as the gate oxide. Thereafter, a silicon is deposited on all areas and refills in the gate hollow region. A planarization process is again performed using the oxide layer as an etch-stopping layer. Subsequently, the oxide layer is removed. S/D/G ion implanted into the polysilicon layer and the silicon layer. Then, the nitride spacers are removed to form dual recessed spaces. Another ion implantation is undertaken into first doped region and in a second doped region, which is in the bottom of the dual recessed spaces. A CVD oxide layer is then deposited on all areas and seals the dual recessed regions and forms the air-gaps. Finally an annealing process is carried out to form the shallow S/D, extended S/D junctions, and the buried contacts.

Abstract translation: 公开了一种形成具有掩埋触点和气隙栅极结构的MOSFET的方法。 该方法包括以下步骤：首先在硅衬底上顺序地形成有衬垫氧化物层和氮化物层的栅极，其具有沟槽隔离。 然后，在所有区域上依次沉积多晶硅层和氧化物层。 随后，实现了使用氮化物层的阻止层的回蚀。 之后，由此去除氮化物层，形成栅极中空区域。 在去除衬垫氧化物层之后，将氮氧化物层再生长成为栅极氧化物。 此后，在所有区域上沉积硅并在栅极中空区域中重新填充。 再次使用氧化物层作为蚀刻停止层进行平坦化处理。 随后，除去氧化物层。 S / D / G离子注入到多晶硅层和硅层中。 然后，去除氮化物间隔物以形成双凹陷空间。 另一种离子注入进入第一掺杂区域和位于双凹槽空间底部的第二掺杂区域。 然后将CVD氧化物层沉积在所有区域上并密封双凹陷区域并形成气隙。 最后，进行退火处理以形成浅的S / D，扩展的S / D结和埋入的触点。

公开(公告)号：US06355540B2

公开(公告)日：2002-03-12

申请号：US09123746

申请日：1998-07-27

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L2176

CPC classification number: H01L21/76232 ,  H01L21/76237

Abstract: The present invention proposes a shallow trench isolation region in a semiconductor substrate for ULSI devices. The trench region includes a thermal oxide film formed on the bottom and the sidewall, a CVD dielectric film formed on the bottom of the thermal oxide film, and a channel stop region formed beneath the bottom of the thermal oxide film. The processes described as follows. Forming a pad oxide/silicon nitride layer on the substrate, the trench region and active area are defined. After silicon spacers are formed, the silicon substrate is recessed to form trench region by using the silicon nitride layer and silicon spacers as etching mask. A channel stopping implantation is performed. Then a thermal oxide film is regrown on the trench surface. After removing the silicon nitride layer, a thick CVD dielectric layer is deposited on the substrate. The dielectric film outside the trench region is removed by a CMP process, and thus the present invention complete.

Abstract translation: 本发明提出了一种用于ULSI器件的半导体衬底中的浅沟槽隔离区。 沟槽区域包括形成在底部和侧壁上的热氧化物膜，形成在热氧化膜的底部上的CVD电介质膜和形成在热氧化膜的底部下方的沟道停止区域。 过程描述如下。 在衬底上形成焊盘氧化物/氮化硅层，限定沟槽区域和有源区域。 在形成硅间隔物之后，通过使用氮化硅层和硅间隔物作为蚀刻掩模，硅衬底凹陷形成沟槽区。 进行通道停止植入。 然后在沟槽表面上重新生长热氧化膜。 在去除氮化硅层之后，在衬底上沉积厚的CVD电介质层。 通过CMP工艺去除沟槽区域外的电介质膜，从而完成本发明。

公开(公告)号：US06329264B1

公开(公告)日：2001-12-11

申请号：US09310888

申请日：1999-05-12

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L28/91

Abstract: In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and is communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer. A hemispherical grained silicon layer is then formed on the first conductive layer. A fourth dielectric layer is formed on the substrate over the hemispherical grained silicon layer and the first conductive layer, and the substrate is planarized to the surface of the third dielectric layer. The fourth dielectric layer and the third dielectric layer are then removed to leave a storage node which is composed of the first conductive layer and the hemispherical grained silicon layer. Finally, a fifth dielectric layer is formed on the storage node, and a second conductive layer is then formed on the fifth dielectric layer to finish the capacitor structure.

Abstract translation: 在用于形成存储单元的粗糙多晶硅冠状电容器的优选实施例中，在半导体衬底上形成第一电介质层。 去除第一电介质层的一部分以限定第一电介质层内的接触孔，其中接触孔向下延伸到衬底中的源极区域。 接下来，形成导电塞，并与接触孔内的源极区域连通。 在第一电介质层和导电插塞上形成第二电介质层，在第二电介质层上形成第三电介质层。 接下来，去除第三电介质层和第二电介质层的部分以限定存储节点开口，其中存储节点开口位于导电插塞上方。 然后形成第一导电层，以一致地覆盖存储节点开口的内表面和第三介电层。 然后在第一导电层上形成半球状的硅层。 在半球形硅层和第一导电层上的基板上形成第四电介质层，并且将基板平面化到第三介电层的表面。 然后去除第四电介质层和第三电介质层以留下由第一导电层和半球形晶粒硅层组成的存储节点。 最后，在存储节点上形成第五电介质层，然后在第五电介质层上形成第二导电层以完成电容器结构。

公开(公告)号：US06303417B1

公开(公告)日：2001-10-16

申请号：US09313085

申请日：1999-05-17

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218238

CPC classification number: H01L21/823892

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of LPD oxide trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. Finally, the standard processes can be employed for fabricating the CMOS transistors on the substrate.

Abstract translation: 本发明公开了一种通过使用更少的掩模计数形成具有自对准平面化双阱的CMOS晶体管的方法。 在半导体衬底上的第一衬垫氧化物层之上形成氮化硅层之后，通过首先注入到半导体衬底中来限定N阱区。 在去除第一光致抗蚀剂层之后，执行第二离子注入以限定P阱区。 接下来，去除氮化硅层和第一衬垫氧化物层。 进行高温长时间退火以形成深双孔。 形成多个LPD氧化物沟槽隔离区域以限定有源区域区域。 在衬底上形成第二衬垫氧化物层。 最后，可以采用标准工艺来制造衬底上的CMOS晶体管。

公开(公告)号：US06294797B1

公开(公告)日：2001-09-25

申请号：US09439432

申请日：1999-11-15

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L2972

CPC classification number: H01L21/28247 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/28035 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66787 ,  H01L29/7833

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first silicon layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract translation: 在半导体衬底上形成栅极绝缘体层，然后在栅极绝缘体层上形成第一硅层。 第一介电层形成在第一硅层之上。 通过去除栅极绝缘体层，第一硅层和第一介电层的一部分来限定栅极区域。 执行使用低能量注入或等离子体浸没的掺杂步骤以掺杂衬底，以在由栅极区域未覆盖的区域下在衬底中形成扩展的源极/漏极结。 在栅极区域的侧壁上形成未掺杂的间隔结构，在半导体衬底上形成第二硅层。 然后去除第一硅层，并执行另一掺杂步骤以掺杂第一硅层和第二硅层。 然后进行一系列处理以在第一硅层和第二硅层上形成金属硅化物层，并且还扩散和激活掺杂的掺杂剂。

公开(公告)号：US06294416B1

公开(公告)日：2001-09-25

申请号：US09307629

申请日：1999-05-07

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218238

CPC classification number: H01L21/823892

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. A high energy and low dose blanket phosphorous is implanted in a semiconductor substrate for forming a punch-through stopping layer of the PMOSFET device. A low energy and low dose blanket BF2 implant then adjust both the threshold voltages of the PMOSFET and NMOSFET. Finally, the standard processes can be employed for fabricating the CMOS transistors.

Abstract translation: 本发明公开了一种通过使用更少的掩模计数形成具有自对准平面化双阱的CMOS晶体管的方法。 在半导体衬底上的第一衬垫氧化物层之上形成氮化硅层之后，通过首先注入到半导体衬底中来限定N阱区。 在去除第一光致抗蚀剂层之后，执行第二离子注入以限定P阱区。 接下来，去除氮化硅层和第一衬垫氧化物层。 进行高温长时间退火以形成深双孔。 形成多个沟槽隔离区域以限定有源区域区域。 在衬底上形成第二衬垫氧化物层。 将高能量和低剂量覆盖磷注入到用于形成PMOSFET器件的穿通停止层的半导体衬底中。 然后，低能量和低剂量覆盖层BF2注入调整PMOSFET和NMOSFET的阈值电压。 最后，可以采用标准工艺来制造CMOS晶体管。

公开(公告)号：US06265263B1

公开(公告)日：2001-07-24

申请号：US09293454

申请日：1999-04-16

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218242

CPC classification number: H01L28/92 ,  H01L27/10852 ,  H01L28/84

Abstract: The method for forming a DRAM capacitor can include the following steps. First, a first dielectric layer is formed on a semiconductor substrate, followed by the formation of a second dielectric layer on the first dielectric layer, and the formation of a third dielectric layer on the second dielectric layer. Next, the first, second, and third dielectric layers are patterned to form a contact hole therein. A doped polysilicon layer is then formed within the contact hole and over the third dielectric layer, followed by the formation of a fourth dielectric layer over the doped polysilicon layer. A patterning step patterns the fourth dielectric layer and the doped polysilicon layer to define a storage node. A hemispherical grained silicon layer is then formed on the fourth dielectric layer, on sidewalls of the storage node, and on the third dielectric layer. The hemispherical grained silicon layer is etched to define a plurality of cavities between grains of the hemispherical grained silicon layer and to expose the fourth dielectric layer through the plurality of cavities. The fourth dielectric layer and the doped polysilicon layer underlying the cavities are then etched to form a porous storage node. The fourth dielectric layer and the third dielectric layer are removed, followed by the formation of a fifth dielectric layer on the porous storage node and the substrate. Finally, a conductive layer is formed on the fifth dielectric layer.

Abstract translation: 形成DRAM电容器的方法可以包括以下步骤。 首先，在半导体衬底上形成第一电介质层，然后在第一电介质层上形成第二电介质层，在第二电介质层上形成第三电介质层。 接下来，对第一，第二和第三电介质层进行图案化以在其中形成接触孔。 然后在接触孔内和第三介电层上形成掺杂多晶硅层，随后在掺杂多晶硅层上形成第四电介质层。 图案化步骤图案化第四介电层和掺杂多晶硅层以限定存储节点。 然后在第四电介质层上，在存储节点的侧壁上和第三电介质层上形成半球形的硅层。 蚀刻半球形晶粒硅层以在半球形硅层的晶粒之间限定多个空腔并且通过多个空腔暴露第四介电层。 然后蚀刻第四电介质层和空腔下面的掺杂多晶硅层以形成多孔存储节点。 去除第四电介质层和第三电介质层，然后在多孔存储节点和衬底上形成第五电介质层。 最后，在第五电介质层上形成导电层。