公开(公告)号：US5909622A

公开(公告)日：1999-06-01

申请号：US720732

申请日：1996-10-01

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/28035 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

公开(公告)号：US5893739A

公开(公告)日：1999-04-13

申请号：US720728

申请日：1996-10-01

申请人： Daniel Kadosh ,  Fred N. Hause ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Fred N. Hause ,  Jon D. Cheek

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/28035 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/7836

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

公开(公告)号：US5888853A

公开(公告)日：1999-03-30

申请号：US905482

申请日：1997-08-01

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/205 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8221 ,  H01L21/8238 ,  H01L29/66772

摘要： An elevated transistor formation includes a plurality of planes upon which transistors are formed. The plurality of transistor planes are formed at multiple relative elevations overlying a substrate wafer using deposited polysilicon to form a substrate between the layers. The polysilicon is deposited in a multiple-grain form to achieve an advantageous balance between deposition rate and substrate quality. In particular, columnar polysilicon is deposited at a temperature of approximately 620.degree. C. and above to achieve a high deposition rate directly overlying a lower-elevation transistor plane. High quality polysilicon is then deposited overlying the columnar polysilicon layer at a temperature of approximately 580.degree. C. or below. The deposition rate for high quality polysilicon is substantially lower than the deposition rate for columnar polysilicon. The highest quality substrate, upon which transistors in an elevated transistor plane are formed, is amorphous polysilicon.

摘要翻译： 升高的晶体管形成包括形成晶体管的多个平面。 多个晶体管平面在沉积的多晶硅上形成在覆盖衬底晶片的多个相对高度处以在层之间形成衬底。 多晶硅以多晶粒形式沉积以实现沉积速率和衬底质量之间的有利平衡。 特别地，在约620℃及以上的温度下沉积柱状多晶硅，以实现直接覆盖较低仰角晶体管平面的高沉积速率。 然后在大约580℃或更低的温度下将高品质多晶硅沉积在柱状多晶硅层上。 高质量多晶硅的沉积速率明显低于柱状多晶硅的沉积速率。 形成高架晶体管平面的晶体管的最高质量的衬底是无定形多晶硅。

公开(公告)号：US5874341A

公开(公告)日：1999-02-23

申请号：US739567

申请日：1996-10-30

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66613 ,  H01L21/28114 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7834

摘要： An IGFET with a gate electrode and a source contact in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, a source contact on the bottom surface, insulative spacers between the gate electrode, the source contact and the sidewalls, and a source and drain adjacent to the bottom surface. A method of forming an IGFET includes forming a trench with first and second opposing sidewalls and a bottom surface in a substrate, forming disposable spacers on the bottom surface, forming a gate insulator material on the bottom surface between the disposable spacers, depositing a gate electrode material on the gate insulator material and disposable spacers, polishing the gate electrode material and then anisotropically etching a lateral portion of the gate electrode material and gate insulator material to form the gate electrode and gate insulator, removing the disposable spacers, forming a first insulative spacer adjacent to the first sidewall, a second insulative spacer adjacent to the gate electrode and second sidewall, and a third insulative spacer adjacent to the gate electrode such that a contact portion of the bottom surface between the first and third insulative spacers is exposed, forming a source and drain in the substrate and adjacent to the bottom surface, and forming source and drain contacts such that the source contact is electrically coupled to the source at the contact portion of the bottom surface and the drain contact is electrically coupled to the drain at the top surface of the substrate. Advantageously, the source contact overlaps the trench, thereby improving packing density.

摘要翻译： 公开了具有沟槽中的栅电极和源极接触的IGFET。 IGFET包括具有相对侧壁和半导体衬底中的底表面的沟槽，底表面上的栅极绝缘体，栅极绝缘体上的栅电极，底表面上的源极接触，栅电极，源极之间的绝缘间隔 接触和侧壁，以及与底表面相邻的源极和漏极。 形成IGFET的方法包括在基板中形成具有第一和第二相对侧壁和底表面的沟槽，在底表面上形成一次性间隔物，在一次性间隔物之间​​的底表面上形成栅极绝缘体材料，沉积栅电极 栅极绝缘体材料和一次性间隔物上的材料，抛光栅电极材料，然后各向异性地蚀刻栅极电极材料和栅极绝缘体材料的侧向部分以形成栅电极和栅极绝缘体，去除一次性间隔物，形成第一绝缘间隔物 与第一侧壁相邻的第二绝缘间隔件，与栅电极和第二侧壁相邻的第二绝缘间隔件，以及与栅电极相邻的第三绝缘间隔件，使得第一和第三绝缘间隔件之间的底表面的接触部分露出，形成 源极和漏极在衬底中并且邻近底面，并且形成 尿液和漏极接触，使得源极接触件在底表面的接触部分处电耦合到源极，并且漏极接触件电耦合到衬底顶表面处的漏极。 有利地，源极接触与沟槽重叠，从而改善了堆积密度。

公开(公告)号：US5852310A

公开(公告)日：1998-12-22

申请号：US67793

申请日：1998-04-28

申请人： Daniel Kadosh ,  Mark I. Garnder ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Mark I. Garnder ,  Jon D. Cheek

IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L27/06 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L21/8221 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0688 ,  H01L2924/0002

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.

摘要翻译： 提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。 因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。 多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同层次的器件之间的互连上。 因此，引入了高性能互连，由此在一个晶体管级内的特征之间使互连尽可能短以达到另一晶体管级内的特征。 互连使用直接在上级晶体管的阱与下部晶体管的阱之间布线的通孔，以便实现相应晶体管的阱之间的直接耦合。 以这种方式的直接耦合使得排列在单独的高程水平上的晶体管的一致操作。 通孔尽可能短，以减少衬底/阱电压电位的任何差异。 这确保了在单独的高程水平上形成的晶体管的可预测的操作。

公开(公告)号：US06949436B2

公开(公告)日：2005-09-27

申请号：US10824428

申请日：2004-04-15

申请人： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

发明人： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

摘要： Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

摘要翻译： 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物下形成复合氧化物/氮化物衬垫来制造。 实施例包括通过解耦等离子体沉积沉积保形氧化物层，通过去耦等离子体沉积沉积共形氮化物层，沉积间隔层然后蚀刻。

公开(公告)号：US06777281B1

公开(公告)日：2004-08-17

申请号：US10214361

申请日：2002-08-08

申请人： Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

发明人： Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

IPC分类号： H01L218238

CPC分类号： H01L29/6659 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823814 ,  H01L29/6656

摘要： A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semi conductor substrate including at least one dopant species-containing region extending to a surface of the substrate; (b) forming a thin liner oxide layer on the surface of the substrate; and (c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：（a）提供半导体衬底，其包括至少一个延伸到衬底表面的含掺杂物种的区域;（b）在衬底的表面上形成薄的衬里氧化物层 基材; 和（c）在细线氧化物层中并入至少一种物质，其至少一种物质，其基本上防止或至少减少其中从至少一种含掺杂物种的区域移动而引起的掺杂物质的偏析。

公开(公告)号：US06764908B1

公开(公告)日：2004-07-20

申请号：US10173770

申请日：2002-06-19

申请人： Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

发明人： Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L21336

CPC分类号： H01L29/1054 ,  H01L21/823807

摘要： A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。 实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动 当前。

公开(公告)号：US06506642B1

公开(公告)日：2003-01-14

申请号：US10020931

申请日：2001-12-19

申请人： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

发明人： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

IPC分类号： H01L218238

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656

摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.

摘要翻译： 亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。 实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物， 在栅电极的已经被去除了第一侧壁间隔物的侧表面上。 实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

公开(公告)号：US06358828B1

公开(公告)日：2002-03-19

申请号：US09118514

申请日：1998-07-17

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L213205

CPC分类号： H01L27/0688

摘要： A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.

摘要翻译： 提供三维集成电路和制造工艺，用于在集成电路的各种级别上产生有源和无源器件。 本方法特别适用于将一个晶体管的源极互连到另一个晶体管的漏极，以形成通常用于核心逻辑单元的串联连接的晶体管。 底层晶体管的结可以连接到上覆晶体管的结，两个晶体管由层间电介质分隔开。 下部晶体管结使用插头导体连接到上层晶体管结。 插头导体，更确切地说，相互连接的连接部分进一步耦合到横向延伸的互连。 互连从插头导体的相互连接点延伸到上覆晶体管的衬底。 因此，覆盖晶体管的源极和衬底可以连接到下面的晶体管的漏极，以便不仅实现串联连接，而且连接内部构造的晶体管的源极和衬底以减少体效应。