公开(公告)号：US06869850B1

公开(公告)日：2005-03-22

申请号：US10326525

申请日：2002-12-20

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/60 ,  H01L29/417 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L29/41775 ,  H01L29/41783

Abstract: In one embodiment, a transistor comprises raised structures over a source region and a drain region. The raised source structures may comprise selectively deposited metal, such as selective tungsten. A self-aligned contact structure formed through a dielectric layer may provide an electrical connection between an overlying structure (e.g., an interconnect line) and the source or drain region. The transistor may further comprise a gate stack having a capping layer over a metal.

Abstract translation: 在一个实施例中，晶体管包括在源极区域和漏极区域上的凸起结构。 升高的源结构可以包括选择性沉积的金属，例如选择性钨。 通过电介质层形成的自对准接触结构可以在上覆结构（例如，互连线）和源极或漏极区之间提供电连接。 晶体管还可以包括在金属上具有覆盖层的栅极堆叠。

公开(公告)号：US06841878B1

公开(公告)日：2005-01-11

申请号：US10672895

申请日：2003-09-26

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/32051 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76838

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract translation: 在一个实施例中，钝化层包括低k电介质。 低k电介质有助于降低金属线在最后一个金属电平的电容，这可能刚好低于钝化水平。 在另一个实施例中，金属线相对较厚。 这有助于降低金属线的电阻并导致RC延迟。

公开(公告)号：US06803330B2

公开(公告)日：2004-10-12

申请号：US09975256

申请日：2001-10-12

Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/518

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas is disclosed. The nitridation process can be carried out at lower temperatures and pressures than a conventional nitrous oxide anneal while still achieving acceptable levels of nitridation. The nitridation process can be conducted at atmospheric or sub-atmospheric pressures. As a result, the nitridation process can be used to form nitrided gate oxide layers in-situ in a CVD furnace. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract translation: 公开了通过用一氧化氮（NO）气体退火预形成的氧化物层来对栅极氧化物层进行氮化的方法。 氮化过程可以在比常规氧化亚氮退火更低的温度和压力下进行，同时仍然达到可接受的氮化水平。 氮化过程可以在大气压或低于大气压的压力下进行。 结果，可以使用氮化工艺在CVD炉中原位形成氮化的栅极氧化物层。 氮化栅氧化层可以在氮化步骤后的第二氧化步骤中任选地再氧化。 然后可以在氮化栅极氧化物层的顶部上或在再氧化和氮化的栅极氧化物层的顶部上沉积栅极电极层（例如，硼掺杂的多晶硅）。

公开(公告)号：US06777307B1

公开(公告)日：2004-08-17

申请号：US10010833

申请日：2001-12-04

Applicant: Krishnaswamy Ramkumar ,  Steven S. Hedayati

Inventor： Krishnaswamy Ramkumar ,  Steven S. Hedayati

IPC: H01L2176

CPC classification number: H01L21/76229 ,  H01L21/3081 ,  H01L21/31053

Abstract: A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

Abstract translation: 提供了一种包括平坦化结构和/或层的方法，使得可以形成减小和更均匀厚度的台阶高度。 特别地，提供了一种方法，其包括抛光地形的上层以暴露第一下层并蚀刻掉第一下层的剩余部分以暴露第二下层。 随后可以将形貌平面化。 因此，用于制造浅沟槽隔离区域的方法可以包括形成延伸穿过布置在半导体衬底上的堆叠的一个或多个沟槽。 这种方法还可以包括在沟槽和层叠层上覆盖电介质，使得沟槽被电介质填充。 然后电介质可以被平坦化，使得保留在沟槽内的电介质的上表面与堆叠的相邻层的上表面共面。

公开(公告)号：US06664120B1

公开(公告)日：2003-12-16

申请号：US10023065

申请日：2001-12-17

Applicant: Sundar Narayanan ,  Krishnaswamy Ramkumar

Inventor： Sundar Narayanan ,  Krishnaswamy Ramkumar

IPC: H01L2166

CPC classification number: H01L22/20 ,  G01N1/32 ,  G01N19/06 ,  H01L22/34

Abstract: A method and a structure are provided for measuring a concentration of an impurity within a layer arranged upon a semiconductor substrate. The method may include exposing the layer and semiconductor substrate to oxidizing conditions and determining a difference in total dielectric thickness above the substrate from before to after exposing the layer and substrate. The difference may be correlated to a concentration of the impurity. In some cases, the method may include designating a plurality of measurement locations on the layer such that a concentration profile of the impurity within the layer may be determined. In some embodiments, exposing the layer and substrate may include forming an oxidized interface between the layer and the semiconductor substrate. Preferably, the oxidized interface is thicker underneath portions of the layer with a lower concentration of the impurity than underneath portions of the layer with a higher concentration of the impurity.

Abstract translation: 提供了一种测量布置在半导体衬底上的层内的杂质浓度的方法和结构。 该方法可以包括将层和半导体衬底暴露于氧化条件，并确定在暴露层和衬底之前至之后的衬底上的总电介质厚度的差异。 该差异可能与杂质的浓度相关。 在一些情况下，该方法可以包括指定层上的多个测量位置，使得可以确定该层内的杂质的浓度分布。 在一些实施例中，暴露层和衬底可以包括在层和半导体衬底之间形成氧化界面。 优选地，具有较低浓度的杂质的层的下部的氧化界面比具有较高浓度杂质的层的下部更厚。

公开(公告)号：US06436799B1

公开(公告)日：2002-08-20

申请号：US09670089

申请日：2000-09-26

Applicant: Krishnaswamy Ramkumar ,  Manuj Rathor

Inventor： Krishnaswamy Ramkumar ,  Manuj Rathor

IPC: H01L21425

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/517

Abstract: A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

公开(公告)号：US06399462B1

公开(公告)日：2002-06-04

申请号：US08885046

申请日：1997-06-30

Applicant: Krishnaswamy Ramkumar ,  Sang S. Kim ,  Sharmin Sadoughi ,  Pamela Trammel ,  Avner Shelem

Inventor： Krishnaswamy Ramkumar ,  Sang S. Kim ,  Sharmin Sadoughi ,  Pamela Trammel ,  Avner Shelem

IPC: H01L2176

CPC classification number: H01L21/7621

Abstract: A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak. The desirable range of slopes for the substrate sidewall is approximately 50°-80° with respect to a nearly planar surface of the substrate in the recess.

Abstract translation: 一种在半导体管芯中形成场氧化物或隔离区域的方法。 对氮化物层（在衬底上方的氧化物层上方）进行构图并随后进行蚀刻，使得氮化物层具有几乎垂直的侧壁。 蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氮化物层的几乎垂直侧壁具有倾斜表面的凹部。 然后使用高压，干燥的氧化气氛将场氧化物生长在凹陷中。 衬底的倾斜侧壁有效地将暴露的衬底的表面远离氮化物层侧壁的边缘移动。 与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。 这导致氧化物侵蚀的减少和几乎不存在的鸟的喙。 相对于凹部中的基板的几乎平坦的表面，衬底侧壁的期望的斜率范围大约为50°-80°。

公开(公告)号：US08691648B1

公开(公告)日：2014-04-08

申请号：US13168711

申请日：2011-06-24

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.

Abstract translation: 提供非易失性半导体存储器及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在覆盖其中形成的沟道区的衬底的表面上形成用于非易失性存储晶体管的栅极，栅极包括电荷俘获层; 和（ii）在非易失性存储晶体管的栅极上形成应变诱导结构，以增加电荷俘获层的电荷保留。 优选地，存储晶体管是包括SONOS栅极堆叠的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）晶体管。 更优选地，存储器还包括在衬底上的逻辑晶体管，并且形成应变诱导结构的步骤包括在逻辑晶体管上形成应变诱导结构的步骤。 还公开了其他实施例。

公开(公告)号：US08680601B2

公开(公告)日：2014-03-25

申请号：US11904475

申请日：2007-09-26

Applicant: Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

Inventor： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC: H01L27/115 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：US08637921B2

公开(公告)日：2014-01-28

申请号：US12005813

申请日：2007-12-27

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract translation: 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，所述方法包括氧化，氮化，再氧化和再纳入。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。