公开(公告)号：US09984932B1

公开(公告)日：2018-05-29

申请号：US15345612

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66545

Abstract: A finFET includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin creating a first semiconductor fin loop by connecting an end of the first semiconductor fin to an end of the second semiconductor fin. A diffusion break isolates the source or the drain, and is positioned about the first semiconductor connector fin and the ends of the first semiconductor fin and the second semiconductor fin. The semiconductor connector fin provides an epitaxial growth surface adjacent the diffusion break. A related method and IC structure are also disclosed.

公开(公告)号：US20180069009A1

公开(公告)日：2018-03-08

申请号：US15259472

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Hui Zang

IPC: H01L27/11 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

公开(公告)号：US09818689B1

公开(公告)日：2017-11-14

申请号：US15137362

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/60

Abstract: A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a first electrode a dielectric of the capacitor, and, depositing a metal within said capacitor trench and said interconnection trench wherein the metal forms a second electrode of the capacitor and also forms an interconnection between layers of an interconnecting structure of a semiconductor device. A semiconductor structure, comprising a dual damascene structure having a capacitor trench for a capacitor, the capacitor including a first electrode, a second electrode, and a high-K dielectric between the first and second electrodes, the high-k dielectric configured to seal the first electrode from the second electrode and from subsequent wiring layers of the interconnecting structure of the semiconductor device, and, an interconnection trench for a metal interconnection to form an interconnection between the interconnecting structure of the semiconductor device.

公开(公告)号：US09799661B1

公开(公告)日：2017-10-24

申请号：US15397004

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: H01L27/108 ,  H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76283 ,  H01L29/0649

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures.

公开(公告)号：US09734897B1

公开(公告)日：2017-08-15

申请号：US15397021

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11 ,  H01L23/522 ,  H01L21/762 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pass gate (PG1) transistor and a second pass gate (PG2) transistor. The at least one CBP facilitates biasing of at least one the PG1 and PG2 transistors during at least one of a read, write or standby operation of the structures.

公开(公告)号：US09620425B1

公开(公告)日：2017-04-11

申请号：US15156822

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Jinping Liu

IPC: H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: A method of adjusting work-function metal thickness includes providing a semiconductor structure having a substrate, the substrate including a first array of fins formed thereon. First spacers are formed having a first spacer thickness on sidewalls of fins of the first array. The thickness of the first spacers is adjusted to provide a second spacer thickness different from the first spacer thickness. First supports are formed between and adjacent the first spacers. The first spacers are removed to form first WF metal trenches defined by the fins of the first array and the first supports. A gate is formed extending laterally across the fins of the first array. First WF metal structures are disposed within the first WF metal trenches within the gate.

公开(公告)号：US09601495B2

公开(公告)日：2017-03-21

申请号：US14814322

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L27/10 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L27/10826 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/10888 ,  H01L28/90 ,  H01L29/66545

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by isolation material, each fin including a source region, a drain region and a channel region therebetween, a first gate and spacers over a portion of each fin, and a second gate and spacers, the second gate encompassing a common end portion of each fin. The first gate and corresponding source and drain regions act as an access transistor, and the second gate and common end portion(s) of the fin(s) act as a storage capacitor, and a top surface of the second gate acts as a plate for the storage capacitor, when multiple cells are arranged in an array.

公开(公告)号：US09601428B2

公开(公告)日：2017-03-21

申请号：US14865589

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Jagar Singh ,  Ashish Baraskar ,  Min-hwa Chi

IPC: H01L23/525 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/283 ,  H01L29/06 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

公开(公告)号：US20170069547A1

公开(公告)日：2017-03-09

申请号：US14845543

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/823814 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

Abstract translation: 本文公开了一种形成CMOS集成电路产品（由第一和第二相对型晶体管组成）的方法，其包括形成靠近第一和第二栅极结构的第一间隔物，形成靠近第一晶体管的第一间隔物的初始第二间隔物 以及在所述第二晶体管上方的第二间隔物层，以及为所述第一晶体管形成第一凸起的外延半导体材料源极/漏极区。 此后，进行第一表面氧化处理，以在第一隆起的外延半导体材料的暴露表面上选择性地形成亲水材料，并在两个晶体管上执行蚀刻处理，以去除初始的第二间隔物和第二间隔物材料层 。

公开(公告)号：US09460996B1

公开(公告)日：2016-10-04

申请号：US14818351

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5223 ,  H01L27/013 ,  H01L28/10 ,  H01L28/60

Abstract: Integrated devices and fabrication methods thereof are presented. The methods include, for instance fabricating an integrated device comprising an inductive portion and a capacitive portion, the integrated device being at least partially embedded within an electrode. The fabricating includes providing a conductive coil at least partially within an insulator layer above a substrate, the conductive coil comprising exposed portions, wherein the inductive portion of the integrated device comprises the conductive coil; covering exposed portions of the conductive coil with a dielectric material; and forming the electrode at least partially around the dielectric covered portions of the conductive coil, the electrode being physically separated from the conductive coil by the dielectric material, wherein the capacitive portion of the integrated device comprises the electrode, the dielectric material, and the conductive coil. In one embodiment, the method further includes: exposing at least one further portion of the conductive coil; and providing another electrode in electrical contact with the at least one exposed further portion of the conductive coil.

Abstract translation: 提出了集成器件及其制造方法。 所述方法包括例如制造包括电感部分和电容部分的集成器件，所述集成器件至少部分地嵌入在电极内。 该制造包括至少部分地在衬底上方的绝缘体层内提供导电线圈，该导电线圈包括暴露部分，其中集成器件的感应部分包括导电线圈; 用介电材料覆盖导电线圈的暴露部分; 以及至少部分地围绕所述导电线圈的电介质覆盖部分形成所述电极，所述电极通过所述电介质材料与所述导电线圈物理分离，其中所述集成器件的所述电容部分包括所述电极，所述电介质材料和所述导电 线圈 在一个实施例中，该方法还包括：暴露导电线圈的至少一个另外的部分; 以及提供与导电线圈的至少一个暴露的另外部分电接触的另一电极。