公开(公告)号：US20140252617A1

公开(公告)日：2014-09-11

申请号：US13786627

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Errol Todd RYAN ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/482

CPC classification number: H01L21/76843 ,  H01L21/76814 ,  H01L21/76826 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.

Abstract translation: 公开了一种调制沉积在半导体衬底中凹陷特征的侧壁和底板上的阻挡层的厚度的工艺。 该方法包括通过在还原气氛中进行退火来改变其上沉积阻挡层的导电特征的表面，以及任选地另外地使形成凹陷特征的侧壁的电介质表面甲硅烷基化。

公开(公告)号：US20140252616A1

公开(公告)日：2014-09-11

申请号：US13785934

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean X. Lin ,  Xunyuan Zhang ,  Ming HE ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract translation: 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US20140246775A1

公开(公告)日：2014-09-04

申请号：US13781921

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76868 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料层上形成由多个间隔开的导电结构构成的非连续层，其中部分 未被多个间隔开的导电结构覆盖的绝缘材料层保持暴露，在非连续层上形成至少一个阻挡层，其中阻挡层接触间隔开的导电结构和该层的暴露部分 绝缘材料，在阻挡层上形成至少一个衬垫层，以及在衬里层上方的沟槽/通孔中形成导电结构。

公开(公告)号：US20140227872A1

公开(公告)日：2014-08-14

申请号：US13766898

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L2221/1063

Abstract: One illustrative method disclosed herein includes performing a first etching process to define a via opening in a layer of insulating material, performing at least one process operation to form a sacrificial liner layer on the sidewalls of the via opening, performing a second etching process to define a trench in the layer of insulating material, wherein the sacrificial liner layer is exposed to the second etching process, after performing the second etching process, performing a third etching process to remove the sacrificial liner layer and, after performing the third etching process, forming a conductive structure in at least the via opening and the trench.

Abstract translation: 本文公开的一种说明性方法包括执行第一蚀刻工艺以在绝缘材料层中限定通孔开口，执行至少一个工艺操作以在通孔开口的侧壁上形成牺牲衬垫层，执行第二蚀刻工艺以界定 在所述绝缘材料层中的沟槽，其中所述牺牲衬垫层在进行所述第二蚀刻工艺之后暴露于所述第二蚀刻工艺，执行第三蚀刻工艺以去除所述牺牲衬垫层，并且在执行所述第三蚀刻工艺之后，形成 至少在通孔开口和沟槽中的导电结构。

公开(公告)号：US08623758B1

公开(公告)日：2014-01-07

申请号：US13657182

申请日：2012-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76852 ,  H01L21/76858 ,  H01L2221/1078 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming an adhesion barrier layer over a dielectric layer formed on a substrate. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. A metal layer is formed over the stress-reducing barrier layer. The metal layer, adhesion barrier layer, and stress-reducing barrier layer define an interconnect metal stack. Recesses are defined in the interconnect metal stack to expose the dielectric layer. The recesses are filled with a dielectric material, wherein a portion of the interconnect metal stack disposed between adjacent recessed filled with dielectric material defines an interconnect structure.

Abstract translation: 一种方法包括在形成在基底上的电介质层上形成粘合阻挡层。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 在应力降低阻挡层上形成金属层。 金属层，粘合阻挡层和应力减小阻挡层限定互连金属叠层。 在互连金属叠层中限定凹陷以暴露电介质层。 这些凹部填充有电介质材料，其中设置在相邻凹陷的填充有电介质材料的互连金属叠层的一部分限定互连结构。

公开(公告)号：US10679937B2

公开(公告)日：2020-06-09

申请号：US15785665

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US10485111B2

公开(公告)日：2019-11-19

申请号：US15647400

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H01L21/768

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

公开(公告)号：US20190318927A1

公开(公告)日：2019-10-17

申请号：US15954066

申请日：2018-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Xunyuan Zhang ,  Frank W. Mont ,  Shao Beng Law

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02

Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

公开(公告)号：US10276689B2

公开(公告)日：2019-04-30

申请号：US15615925

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Ruilong Xie ,  Xunyuan Zhang ,  Hui Zang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

公开(公告)号：US20190088500A1

公开(公告)日：2019-03-21

申请号：US15705956

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Mark V. Raymond ,  Errol Todd Ryan ,  Nicholas V. LiCausi

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.