公开(公告)号：US11063140B2

公开(公告)日：2021-07-13

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L27/082

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US20210098612A1

公开(公告)日：2021-04-01

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US20210091200A1

公开(公告)日：2021-03-25

申请号：US16788914

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

IPC: H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.

公开(公告)号：US12159910B2

公开(公告)日：2024-12-03

申请号：US17671879

申请日：2022-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili Raghunathan ,  Vibhor Jain ,  Sebastian Ventrone ,  Johnatan Kantarovsky ,  Yves Ngu

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/735

Abstract: Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.

公开(公告)号：US20240231173A1

公开(公告)日：2024-07-11

申请号：US18094716

申请日：2023-01-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Yusheng Bian ,  Shesh Mani Pandey ,  Abdelsalam Aboketaf ,  Ravi Prakash Srivastava

IPC: G02F1/21 ,  F25B21/04 ,  G02F1/225 ,  H10N10/17 ,  H10N10/851 ,  H10N10/852

CPC classification number: G02F1/212 ,  F25B21/04 ,  G02F1/2257 ,  H10N10/17 ,  H10N10/852 ,  H10N10/8556 ,  G02F2202/10 ,  G02F2203/50

Abstract: Structures including an optical phase shifter and methods of forming a structure including an optical phase shifter. The structure comprises an optical phase shifter including a waveguide core having a first branch and a second branch laterally spaced from the first branch. The structure further comprises a thermoelectric device including a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit. The first plurality of pillars and the second plurality of pillars disposed adjacent to the first branch of the waveguide core, the first plurality of pillars comprises an n-type semiconductor material, and the second plurality of pillars comprises a p-type semiconductor material.

公开(公告)号：US20240192442A1

公开(公告)日：2024-06-13

申请号：US18079523

申请日：2022-12-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ravi Prakash Srivastava ,  Yusheng Bian ,  Shesh Mani Pandey ,  Vibhor Jain

IPC: G02B6/122 ,  G02B6/136

CPC classification number: G02B6/1228 ,  G02B6/136

Abstract: Structures for an edge coupler and methods of forming a structure for an edge coupler. The structure comprises a substrate, a dielectric layer over the substrate, and a waveguide core over the substrate. The structure further comprises an airgap that extends at least partially through the dielectric layer and that surrounds a plurality of sides of a portion of the waveguide core.

公开(公告)号：US20240159701A1

公开(公告)日：2024-05-16

申请号：US17987543

申请日：2022-11-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson Holt ,  Bartlomiej Jan Pawlak ,  Vibhor Jain

IPC: G01N27/414

CPC classification number: G01N27/4148

Abstract: Structures for an ion-sensitive field-effect transistor and methods of forming same. The structure comprises a semiconductor substrate, a microfluidic channel above the semiconductor substrate, a semiconductor layer including a portion positioned as a sensing layer in the microfluidic channel, a first electrical connection coupled to the portion of the semiconductor layer, and a second electrical connection coupled to the semiconductor substrate. The portion of the semiconductor layer is spaced above the semiconductor substrate.

公开(公告)号：US11935923B2

公开(公告)日：2024-03-19

申请号：US17525256

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Vibhor Jain ,  Judson R. Holt ,  Jagar Singh ,  Mankyu Yang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/735 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

公开(公告)号：US11862717B2

公开(公告)日：2024-01-02

申请号：US17456395

申请日：2021-11-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Alvin J. Joseph ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/66 ,  H01L29/735 ,  H01L29/08 ,  H01L29/15 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/158 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

公开(公告)号：US11804543B2

公开(公告)日：2023-10-31

申请号：US17540339

申请日：2021-12-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Judson R. Holt

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7391 ,  H01L29/66356

Abstract: Structures for a diode and methods of fabricating a structure for a diode. The structure includes a layer comprised of a semiconductor material. The layer includes a first section, a second section, and a third section laterally positioned between the first section and the second section. The structure includes a first terminal having a raised semiconductor layer on the first section of the layer, a second terminal including a portion on the second section of the layer, and a gate on the third section of the layer.