公开(公告)号：US20080283839A1

公开(公告)日：2008-11-20

申请号：US11834886

申请日：2007-08-07

申请人： Hiroshi Watanabe ,  Fumitaka Arai

发明人： Hiroshi Watanabe ,  Fumitaka Arai

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer.

摘要翻译： 非易失性半导体存储装置包括基板，形成在基板上的第一绝缘层，在第一绝缘层上由多晶硅形成的半导体层，形成在第一绝缘层上以穿过半导体层的一对导体区域，以及 夹在半导体层的一部分上，由金属或硅化物形成，形成在夹在一对导体区域之间的半导体层的一部分上的隧道层，形成在隧道层上的电荷存储层，第二绝缘层 形成在电荷存储层上的层，以及形成在第二绝缘层上的控制栅极。

公开(公告)号：US07432561B2

公开(公告)日：2008-10-07

申请号：US11608393

申请日：2006-12-08

申请人： Makoto Mizukami ,  Fumitaka Arai

发明人： Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

摘要翻译： 具有多个存储单元晶体管的线性排列的非易失性半导体存储器包括：具有第一导电类型的第一半导体层; 第二半导体层，设置在所述第一半导体层上以防止杂质从所述第一半导体层扩散到所述第二半导体层上方的区域; 以及设置在所述第二半导体层上的第三半导体层，包括具有第二导电类型的第一源极区域，具有第二导电类型的第一漏极区域和具有用于每个存储单元晶体管的第二导电类型的第一沟道区域。

公开(公告)号：US20080179677A1

公开(公告)日：2008-07-31

申请号：US12022382

申请日：2008-01-30

申请人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

发明人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/105 ,  H01L21/84 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/1203

摘要： Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According to one aspect, there is provided a semiconductor storage device includes a first semiconductor region provided in a semiconductor substrate including a buried insulator having opening portions, a second semiconductor region without including buried insulator, a plurality of first semiconductor element devices disposed above the buried insulator, a plurality of second semiconductor element devices each disposed in a region including a region above the opening portion of the buried insulator, and a plurality of third semiconductor element devices disposed in the second semiconductor region.

摘要翻译： 其中具有不同功能的多个半导体元件器件设置在部分SOI衬底的适当区域中并且每个栅绝缘体和每个栅电极之间的界面形成为相同水平的半导体存储器件，并且其制造方法被公开 。 根据一个方面，提供一种半导体存储装置，包括设置在包括具有开口部分的埋入式绝缘体的半导体衬底中的第一半导体区域，不包括埋入绝缘体的第二半导体区域，设置在掩埋层上方的多个第一半导体元件器件 绝缘体，多个第二半导体元件器件，每个第二半导体元件器件设置在包括所述埋入绝缘体的开口部分上方的区域的区域中，以及设置在所述第二半导体区域中的多个第三半导体元件器件。

公开(公告)号：US20080121965A1

公开(公告)日：2008-05-29

申请号：US11870114

申请日：2007-10-10

申请人： Atsuhiro SATO ,  Fumitaka Arai ,  Yasuhiko Matsunaga

发明人： Atsuhiro SATO ,  Fumitaka Arai ,  Yasuhiko Matsunaga

IPC分类号： H01L27/105

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a plurality of memory cell transistors which are connected in series to one another with a first gate spacing, every two adjacent transistors of the memory cell transistors sharing a source/drain diffusion layer, and a first select gate transistor which shares a source/drain diffusion layer with an endmost memory cell transistor that is located at one end of the series connection of the memory cell transistors and is adjacent to that memory cell transistor with a second gate spacing. The second gate spacing is set larger than the first gate spacing and the source/drain diffusion layer shared by the endmost memory cell transistor and the first select gate transistor contains a region which is higher in impurity concentration than the source/drain diffusion layer shared by two adjacent memory cell transistors.

摘要翻译： 本发明的一个方面的非易失性半导体存储器包括以第一栅极间隔彼此串联连接的多个存储单元晶体管，存储单元晶体管的每两个相邻晶体管共享源极/漏极扩散层，以及 共享源/漏扩散层的第一选择栅极晶体管，其具有位于存储单元晶体管的串联连接的一端并且具有第二栅极间隔的该存储单元晶体管的最末端的存储单元晶体管。 第二栅极间隔被设定为大于第一栅极间隔，并且由最末端存储单元晶体管共享的源极/漏极扩散层，并且第一选择栅极晶体管包含杂质浓度高于源极/漏极扩散层所分配的源极/漏极扩散层的区域 两个相邻的存储单元晶体管。

公开(公告)号：US20080061357A1

公开(公告)日：2008-03-13

申请号：US11980561

申请日：2007-10-31

申请人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

发明人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

摘要翻译： 一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。 该装置还包括上接触孔，下接触孔和接触塞。 上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。 底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。 下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。 下接触孔的上部具有与沟槽相同的宽度。 接触塞设置在上接触孔和下接触孔中。

公开(公告)号：US20080012061A1

公开(公告)日：2008-01-17

申请号：US11687758

申请日：2007-03-19

申请人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮置栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：US07310270B2

公开(公告)日：2007-12-18

申请号：US11737154

申请日：2007-04-19

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选择的存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

公开(公告)号：US20070196986A1

公开(公告)日：2007-08-23

申请号：US11676814

申请日：2007-02-20

申请人： Masayuki Ichige ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Masayuki Ichige ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/0638

摘要： A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring, and a peripheral circuit region around the second guard ring and including second pattern, the method including exposing the resist film by multiple exposure including first and second exposures for forming latent images corresponding to the first and second patterns, a boundary area of the multiple exposure being set on the isolation region, on the first or second guard ring, or on an area between the first guard ring and the memory cell region, forming a resist pattern by developing the resist film, and etching the substrate with the resist pattern as a mask.

摘要翻译： 一种半导体器件的制造方法，包括：衬底，包括第一图案的存储单元区域，存储单元周围的第一保护环，第一保护环周围的第二保护环，第一和第二保护环之间的隔离区域， 电路区域，并且包括第二图案，所述方法包括通过多次曝光曝光所述抗蚀剂膜，所述多次曝光包括用于形成对应于所述第一和第二图案的潜像的第一和第二曝光，所述多次曝光的边界区域设置在 在第一或第二保护环上或第一保护环和存储单元区域之间的区域上，通过显影抗蚀剂膜形成抗蚀剂图案，并用抗蚀剂图案作为掩模蚀刻基板。

公开(公告)号：US20070177431A1

公开(公告)日：2007-08-02

申请号：US11447963

申请日：2006-06-07

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

摘要翻译： 公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体 存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。 在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。 在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

公开(公告)号：US07122858B2

公开(公告)日：2006-10-17

申请号：US11118478

申请日：2005-05-02

申请人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma ,  Riichiro Shirota ,  Akira Shimizu

发明人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma ,  Riichiro Shirota ,  Akira Shimizu

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.