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    PROCESS FOR MAKING FINFET DEVICE WITH BODY CONTACT AND BURIED OXIDE JUNCTION ISOLATION
    83.
    发明申请
    PROCESS FOR MAKING FINFET DEVICE WITH BODY CONTACT AND BURIED OXIDE JUNCTION ISOLATION 有权
    用身体接触和氧化锌结隔离制造FINFET器件的工艺

    公开(公告)号：US20080224213A1

    公开(公告)日：2008-09-18

    申请号：US11686013

    申请日：2007-03-14

    申请人： Thomas W. Dyer ,  Haining S. Yang

    发明人： Thomas W. Dyer ,  Haining S. Yang

    IPC分类号： H01L21/3205 ,  H01L27/01

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： There is a FinFET device. The device has a silicon substrate, an oxide layer, and a polysilicone gate. The silicon substrate defines a planar body, a medial body, and a fin. The planar body, the medial body, and the fin are integrally connected. The medial body connects the planar body and the fine. The planar body extends generally around the medial body. The fin is situated to extend substantially from a first side of the substrate to an opposing second side of the substrate. The fin is substantially perpendicularly disposed with respect to the planar body. The first oxide layer is situated on the planar body between the planar body and the fine. The oxide layer extends substantially around the medial body. The polysilicone gate is situated on the oxide layer to extend substantially from a third side to an opposing fourth side of the substrate. The gate is situated to extend across the fin proximal to a medial portion of an upper surface of the fine. There is also a process for making a FinFET device.

    摘要翻译： 有一个FinFET器件。 该器件具有硅衬底，氧化物层和多晶硅栅极。 硅衬底限定平面体，中间体和翅片。 平面体，内侧体和翅片整体连接。 内侧身体连接平面体和精细。 平面体通常围绕内侧身体延伸。 翅片位于基本上从基板的第一侧延伸到基板的相对的第二侧。 翅片相对于平面主体基本垂直设置。 第一氧化物层位于平面体与平面体之间。 氧化物层基本上围绕内侧本体延伸。 多晶硅栅极位于氧化物层上，基本上从衬底的第三侧延伸到相对的第四侧。 门被设置为延伸穿过鳍片靠近微细上表面的中间部分。 还有一种制造FinFET器件的过程。

    SUB-LITHOGRAPHIC INTERCONNECT PATTERNING USING SELF-ASSEMBLING POLYMERS
    84.
    发明申请
    SUB-LITHOGRAPHIC INTERCONNECT PATTERNING USING SELF-ASSEMBLING POLYMERS 失效
    使用自组装聚合物的次平面互连图案

    公开(公告)号：US20080182402A1

    公开(公告)日：2008-07-31

    申请号：US11627488

    申请日：2007-01-26

    申请人： Wai-Kin Li ,  Haining S. Yang

    发明人： Wai-Kin Li ,  Haining S. Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  Y10S438/947 ,  Y10S977/888 ,  Y10S977/895 ,  Y10S977/90

    摘要： The present invention is directed to the formation of sublithographic features in a semiconductor structure using self-assembling polymers. The self-assembling polymers are formed in openings in a hard mask, annealed and then etched, followed by etching of the underlying dielectric material. At least one sublithographic feature is formed according to this method. Also disclosed is an intermediate semiconductor structure in which at least one interconnect wiring feature has a dimension that is defined by a self-assembled block copolymer.

    摘要翻译： 本发明涉及使用自组装聚合物在半导体结构中形成亚光刻特征。 自组装聚合物形成在硬掩模的开口中，退火然后蚀刻，然后蚀刻下面的介电材料。 根据该方法形成至少一个亚光刻特征。 还公开了一种中间半导体结构，其中至少一个互连布线特征具有由自组装嵌段共聚物限定的尺寸。

    STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE
    85.
    发明申请
    STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中形成改进隔离的结构和方法

    公开(公告)号：US20080171420A1

    公开(公告)日：2008-07-17

    申请号：US11622057

    申请日：2007-01-11

    申请人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

    发明人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823878 ,  H01L21/76227 ,  H01L21/76237

    摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.

    摘要翻译： 公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。 衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。 硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。 在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

    SUB-LITHOGRAPHIC FACETING FOR MOSFET PERFORMANCE ENHANCEMENT
    86.
    发明申请
    SUB-LITHOGRAPHIC FACETING FOR MOSFET PERFORMANCE ENHANCEMENT 审中-公开
    用于MOSFET性能增强的次平面成像

    公开(公告)号：US20080169535A1

    公开(公告)日：2008-07-17

    申请号：US11622588

    申请日：2007-01-12

    申请人： Shahid A. Butt ,  Thomas W. Dyer ,  Oh-Jung Kwon ,  Jack A. Mandelman ,  Haining S. Yang

    发明人： Shahid A. Butt ,  Thomas W. Dyer ,  Oh-Jung Kwon ,  Jack A. Mandelman ,  Haining S. Yang

    IPC分类号： H01L29/06 ,  H01L21/311

    CPC分类号： H01L21/3086 ,  H01L21/28123 ,  H01L21/3088 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/78

    摘要： The present invention provides structures and methods for providing multiple parallel V-shaped faceted grooves with sub-lithographic widths on a semiconductor substrate for enhanced performance MOSFETs. A self-aligning self-assembling material is used to pattern multiple parallel sub-lithographic lines. By employing an anisotropic etch that produces crystallographic facets on a semiconductor surface, multiple adjoining parallel V-shaped grooves with sub-lithographic groove widths are formed. While providing enhanced mobility for the MOSFET, the width of the MOSFET is not limited by the depth of focus in subsequent lithographic steps or the thickness of semiconductor layer above a BOX layer due to the sub-lithographic widths of the V-shaped grooves and the consequent reduction in the variation of the vertical profile. Also, the MOSFET has a well defined threshold voltage due to the narrow widths of each facet.

    摘要翻译： 本发明提供了用于在半导体衬底上提供具有亚光刻宽度的多个平行V形刻面槽以提高性能MOSFET的结构和方法。 使用自对准自组装材料来对多个平行的次平版印刷线进行图案化。 通过采用在半导体表面上产生结晶小面的各向异性蚀刻，形成具有亚光刻槽宽度的多个相邻的平行V形槽。 在为MOSFET提供增强的移动性的同时，MOSFET的宽度不受后续光刻步骤中的深度深度或BOX层上方的半导体层厚度的限制，这是由于V形沟槽的次平版印刷宽度和 从而导致垂直剖面变化的减小。 此外，由于每个刻面的窄宽度，MOSFET具有明确的阈值电压。

    Method of fabricating strained channel field effect transistor pair having underlapped dual liners
    87.
    发明授权
    Method of fabricating strained channel field effect transistor pair having underlapped dual liners 有权
    制造具有双重衬垫的应变通道场效应晶体管对的方法

    公开(公告)号：US07285488B2

    公开(公告)日：2007-10-23

    申请号：US11492455

    申请日：2006-07-25

    申请人： Haining S. Yang

    发明人： Haining S. Yang

    IPC分类号： H01L21/4763 ,  H01L23/52

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided of forming contact vias. A dielectric region is formed to overlie substantially all of a transistor structure, the dielectric region having a substantially planar upper surface. A dielectric barrier layer is formed to overlie the upper surface of the dielectric region, the dielectric barrier layer being adapted to substantially prevent diffusion of one or more materials from above the dielectric barrier layer into the dielectric region. A first contact via is formed to extend through the dielectric barrier layer and the dielectric region to provide conductive communication with a conductive member of the transistor structure. A second contact via is formed to extend through the dielectric barrier layer and the dielectric region to provide conductive communication with one of a source region or a drain region of the transistor structure.

    摘要翻译： 提供形成接触孔的方法。 形成电介质区域以覆盖基本上所有的晶体管结构，所述电介质区域具有基本平坦的上表面。 介电阻挡层被形成为覆盖在电介质区域的上表面上，电介质阻挡层适于基本上防止一种或多种材料从电介质阻挡层上方扩散到电介质区域中。 形成第一接触通孔以延伸穿过电介质阻挡层和电介质区域，以提供与晶体管结构的导电构件的导电连通。 第二接触通孔被形成为延伸通过电介质阻挡层和电介质区域以提供与晶体管结构的源极区域或漏极区域之一的导电连通。

    Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
    88.
    发明授权
    Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern 失效
    制造半导体集成电路容忍金属接触图形不对准的结构和方法

    公开(公告)号：US07217647B2

    公开(公告)日：2007-05-15

    申请号：US10904330

    申请日：2004-11-04

    申请人： Haining S. Yang

    发明人： Haining S. Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/823468 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823475

    摘要： Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate.

    摘要翻译： 公开了一种制造场效应晶体管的方法。 在该方法中，形成半导体衬底的顶表面上的栅极叠层，然后在栅极堆叠的侧壁上形成第一间隔物。 接下来，将与第一间隔物自对准的硅化物沉积在半导体衬底中的/或上。 随后，形成覆盖第一间隔物的表面的第二间隔物，以及至少栅极叠层，第二间隔物和硅化物之间的接触衬垫。 然后沉积接触衬垫上的层间电介质。 接下来，形成金属接触开口以使接触衬里暴露在硅化物上。 最后，将开口延伸穿过接触衬垫以暴露硅化物而不暴露衬底。

    Structure and method to improve SRAM stability without increasing cell area or off current
    89.
    发明授权
    Structure and method to improve SRAM stability without increasing cell area or off current 失效
    提高SRAM稳定性的结构和方法，不增加单元面积或关断电流

    公开(公告)号：US06984564B1

    公开(公告)日：2006-01-10

    申请号：US10710184

    申请日：2004-06-24

    申请人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

    发明人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

    IPC分类号： H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

    摘要： An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress on the pull-down and pass gate transistors in a version designed to reduce the cell size and increase speed of operation.

    摘要翻译： CMOS集成电路中的SRAM在其晶体管的沟道上受到应力; 上拉和栅极晶体管中的压应力和下拉晶体管中的拉伸应力，旨在提高稳定性; 并且上拉晶体管中的压应力和下拉和通过栅极晶体管中的拉伸应力在设计成减小电池尺寸并增加操作速度的版本中。

    Complementary transistors having different source and drain extension spacing controlled by different spacer sizes
    90.
    发明授权
    Complementary transistors having different source and drain extension spacing controlled by different spacer sizes 有权

    公开(公告)号：US06946709B2

    公开(公告)日：2005-09-20

    申请号：US10726326

    申请日：2003-12-02

    申请人： Haining S. Yang

    发明人： Haining S. Yang

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/7843 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0615 ,  H01L29/1083 ,  H01L29/6656

    摘要： Disclosed is a method of forming an integrated circuit structure having first-type transistors, such as P-type field effect transistors (PFETs) and complementary second-type transistors, such as N-type field effect transistors (NFETs) on the same substrate. More specifically, the invention forms gate conductors above channel regions in the substrate, sidewall spacers adjacent the gate conductors, and source and drain extensions in the substrate. The sidewall spacers are larger (extend further from the gate conductor) in the PFETs than in the NFETs. The sidewall spacers align the source and drain extensions during the implanting process. Therefore, the larger sidewall spacers position (align) the source and drain implants further from the channel region for the PFETs when compared to the NFETs. Then, during the subsequent annealing processes, the faster moving PFET impurities will be restrained from diffusing too far into the channel region under the gate conductor. This prevents the short channel effect that occurs when the source and drain impurities extend too far beneath the gate conductor and short out the channel region.