公开(公告)号：US07875921B2

公开(公告)日：2011-01-25

申请号：US12692197

申请日：2010-01-22

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

公开(公告)号：US20100117140A1

公开(公告)日：2010-05-13

申请号：US12692197

申请日：2010-01-22

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US07419879B2

公开(公告)日：2008-09-02

申请号：US11329623

申请日：2006-01-11

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

公开(公告)号：US07341912B2

公开(公告)日：2008-03-11

申请号：US11301854

申请日：2005-12-13

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

摘要翻译： 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US07214588B2

公开(公告)日：2007-05-08

申请号：US11247814

申请日：2005-10-11

申请人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

发明人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： In a floating gate memory cell including a floating gate separated from an active region by a tunnel isolation region, a first one of the active region and the floating gate comprises a portion that protrudes towards a second one of the active region and the floating gate. In some embodiments, the protruding portion tapers toward the second one of the active region and the floating gate. The tunnel insulation layer may be narrowed at the protruding portion. Protruding portions may be formed on both the floating gate and the active region.

摘要翻译： 在包括通过隧道隔离区域与有源区域分离的浮动栅极的浮动栅极存储单元中，有源区域和浮置栅极中的第一个包括朝向有源区域和浮置栅极中的第二个突出的部分。 在一些实施例中，突出部分朝向有源区域和浮动栅极中的第二个逐渐变细。 隧道绝缘层可以在突出部分变窄。 突出部分可以形成在浮动栅极和有源区域两者上。

公开(公告)号：US20060186460A1

公开(公告)日：2006-08-24

申请号：US11301854

申请日：2005-12-13

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

摘要翻译： 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US20060128123A1

公开(公告)日：2006-06-15

申请号：US11334918

申请日：2006-01-19

申请人： Sung-min Kim ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Shin-ae Lee ,  Seong-ho Kim

发明人： Sung-min Kim ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Shin-ae Lee ,  Seong-ho Kim

IPC分类号： H01L21/20

CPC分类号： H01L21/76264 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78639 ,  H01L29/78654

摘要： An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.

摘要翻译： 集成电路结构可以包括隔离结构，其将集成电路基板的有源区域与相邻的有源区域隔离，以及从隔离结构延伸到有源区域下方的绝缘层。 外延硅层从有源区延伸穿过绝缘层到绝缘层下方的衬底。

公开(公告)号：US20060046370A1

公开(公告)日：2006-03-02

申请号：US11210820

申请日：2005-08-25

申请人： Yong-chul Oh ,  Wook-je Kim ,  Dong-gun Park ,  Woun-suck Yang

发明人： Yong-chul Oh ,  Wook-je Kim ,  Dong-gun Park ,  Woun-suck Yang

IPC分类号： H01L21/8238 ,  H01L21/425 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L21/28061 ,  H01L21/3212 ,  H01L21/823842

摘要： A method of manufacturing a MOS transistor with a void-free gate electrode is provided. A gate oxide film may be formed on a semiconductor, and a poly silicon film for a gate electrode may be deposited on the gate oxide film. P-type impurities may be implanted into the poly silicon film, and a thickness of the poly silicon film may be removed by chemical mechanical polishing.

摘要翻译： 提供一种制造具有无空隙栅电极的MOS晶体管的方法。 可以在半导体上形成栅极氧化膜，并且可以在栅极氧化膜上沉积用于栅电极的多晶硅膜。 可以将P型杂质注入到多晶硅膜中，并且可以通过化学机械抛光去除多晶硅膜的厚度。

公开(公告)号：US06998669B2

公开(公告)日：2006-02-14

申请号：US10726768

申请日：2003-12-03

申请人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

发明人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： In a floating gate memory cell including a floating gate separated from an active region by a tunnel isolation region, a first one of the active region and the floating gate comprises a portion that protrudes towards a second one of the active region and the floating gate. In some embodiments, the protruding portion tapers toward the second one of the active region and the floating gate. The tunnel insulation layer may be narrowed at the protruding portion. Protruding portions may be formed on both the floating gate and the active region.

摘要翻译： 在包括通过隧道隔离区域与有源区域分离的浮动栅极的浮动栅极存储单元中，有源区域和浮置栅极中的第一个包括朝向有源区域和浮置栅极中的第二个突出的部分。 在一些实施例中，突出部分朝向有源区域和浮动栅极中的第二个逐渐变细。 隧道绝缘层可以在突出部分变窄。 突出部分可以形成在浮动栅极和有源区域两者上。

公开(公告)号：US20060029887A1

公开(公告)日：2006-02-09

申请号：US11094623

申请日：2005-03-30

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

IPC分类号： G03F7/00

CPC分类号： H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

摘要翻译： 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。