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公开(公告)号:US20250112200A1
公开(公告)日:2025-04-03
申请号:US18374559
申请日:2023-09-28
Applicant: Intel Corporation
Inventor: Adel Elsherbini , Kimin Jun , Feras Eid , Thomas Sounart , Yi Shi , Shawna Liff , Johanna Swan , Michael Baker , Bhaskar Jyoti Krishnatreya , Chien-An Chen
IPC: H01L23/00 , H01L21/56 , H01L23/31 , H01L23/498 , H01L25/065
Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
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公开(公告)号:US20250112199A1
公开(公告)日:2025-04-03
申请号:US18374520
申请日:2023-09-28
Applicant: Intel Corporation
Inventor: Thomas Sounart , Feras Eid , Adel Elsherbini , Yi Shi , Michael Baker , Kimin Jun , Wenhao Li
IPC: H01L23/00 , H01L25/065
Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.
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公开(公告)号:US20250105053A1
公开(公告)日:2025-03-27
申请号:US18473711
申请日:2023-09-25
Applicant: Intel Corporation
Inventor: Adel Elsherbini , Han Wui Then , Feras Eid , James E. Jaussi , Ganesh Balamurugan , Thomas L. Sounart , Johanna Swan , Henning Braunisch , Tushar Kanti Talukdar , Shawna M. Liff
IPC: H01L21/762 , G02B6/30 , G02B6/43 , H01L21/67 , H01L21/683 , H01L21/768
Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or electronic integrated circuits. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
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公开(公告)号:US20250105046A1
公开(公告)日:2025-03-27
申请号:US18473905
申请日:2023-09-25
Applicant: Intel Corporation
Inventor: Adel Elsherbini , Thomas L. Sounart , Feras Eid , Tushar Kanti Talukdar , Brandon M. Rawlings , Andrey Vyatskikh , Carlos Bedoya Arroyave , Kimin Jun , Shawna M. Liff , Grant M. Kloster , Richard F. Vreeland , William P. Brezinski , Johanna Swan
IPC: H01L21/683 , H01L23/00 , H01L25/065
Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a layer of integrated circuit (IC) components is received, and a second substrate with one or more adhesive areas is received. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
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公开(公告)号:US20250105025A1
公开(公告)日:2025-03-27
申请号:US18474043
申请日:2023-09-25
Applicant: Intel Corporation
Inventor: Thomas L. Sounart , Adel Elsherbini , Feras Eid , Tushar Kanti Talukdar
Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of integrated circuit (IC) components over the release layer is received, and a second substrate with one or more adhesive areas is received. The release layer on the first substrate is weakened. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
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公开(公告)号:US12224261B2
公开(公告)日:2025-02-11
申请号:US17488174
申请日:2021-09-28
Applicant: Intel Corporation
Inventor: Shawna Liff , Adel Elsherbini , Johanna Swan , Nagatoshi Tsunoda , Jimin Yao
IPC: H01L23/00 , H01L21/48 , H01L23/498
Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.
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公开(公告)号:US12199012B2
公开(公告)日:2025-01-14
申请号:US16914066
申请日:2020-06-26
Applicant: Intel Corporation
Inventor: Adel Elsherbini , Stephen Morein , Feras Eid , Georgios Dogiamis
IPC: H01L23/467 , C23C24/04 , H01L21/48 , H01L23/373 , H01L23/473 , F28D1/03 , F28D21/00
Abstract: A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.
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公开(公告)号:US20240063136A1
公开(公告)日:2024-02-22
申请号:US17891560
申请日:2022-08-19
Applicant: Intel Corporation
Inventor: Haris Khan Niazi , Yi Shi , Adel Elsherbini , Xavier Brun , Georgios Dogiamis , Thomas Brown , Omkar Karhade
IPC: H01L23/544
CPC classification number: H01L23/544 , H01L2223/54426 , H01L2223/54473
Abstract: An integrated circuit (IC) device comprises an array comprising rows and columns of conductive interconnect pads. At least one optical alignment fiducial region is distinct from the array and comprises a fiducial pattern, wherein the fiducial pattern comprises a first group of pads contiguous to a second group of pads, and wherein a width of a space between nearest pads of the first and second groups is wider than the spaces between pads within each group.
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公开(公告)号:US11830831B2
公开(公告)日:2023-11-28
申请号:US16327810
申请日:2016-09-23
Applicant: INTEL CORPORATION
Inventor: Georgios Dogiamis , Sasha Oster , Johanna Swan , Shawna Liff , Adel Elsherbini , Telesphor Kamgaing , Aleksandar Aleksov
CPC classification number: H01L23/66 , H01P3/121 , H01L2223/6627
Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.
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90.
公开(公告)号:US11823972B2
公开(公告)日:2023-11-21
申请号:US16040746
申请日:2018-07-20
Applicant: Intel Corporation
Inventor: Feras Eid , Adel Elsherbini , Johanna Swan
IPC: H01L23/367 , H01L25/065 , H01L23/498 , H01L23/373
CPC classification number: H01L23/367 , H01L23/3737 , H01L23/49838 , H01L25/0657 , H01L2225/06513 , H01L2225/06517
Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.
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