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    SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES
    82.
    发明申请
    SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES 有权

    公开(公告)号：US20250112199A1

    公开(公告)日：2025-04-03

    申请号：US18374520

    申请日：2023-09-28

    Applicant: Intel Corporation

    Inventor： Thomas Sounart ,  Feras Eid ,  Adel Elsherbini ,  Yi Shi ,  Michael Baker ,  Kimin Jun ,  Wenhao Li

    IPC: H01L23/00 ,  H01L25/065

    Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.

    BLANKET WAFER LASER PRE-EXPOSURE FOR FAST SELECTIVE LAYER TRANSFERS
    85.
    发明申请
    BLANKET WAFER LASER PRE-EXPOSURE FOR FAST SELECTIVE LAYER TRANSFERS 有权

    公开(公告)号：US20250105025A1

    公开(公告)日：2025-03-27

    申请号：US18474043

    申请日：2023-09-25

    Applicant: Intel Corporation

    Inventor： Thomas L. Sounart ,  Adel Elsherbini ,  Feras Eid ,  Tushar Kanti Talukdar

    IPC: H01L21/50 ,  H01L21/78 ,  H01L23/00

    Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of integrated circuit (IC) components over the release layer is received, and a second substrate with one or more adhesive areas is received. The release layer on the first substrate is weakened. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

    Mixed hybrid bonding structures and methods of forming the same
    86.
    发明授权
    Mixed hybrid bonding structures and methods of forming the same 有权

    公开(公告)号：US12224261B2

    公开(公告)日：2025-02-11

    申请号：US17488174

    申请日：2021-09-28

    Applicant: Intel Corporation

    Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

    IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

    Semiconductor package including a modular side radiating waveguide launcher
    89.
    发明授权
    Semiconductor package including a modular side radiating waveguide launcher 有权

    公开(公告)号：US11830831B2

    公开(公告)日：2023-11-28

    申请号：US16327810

    申请日：2016-09-23

    Applicant: INTEL CORPORATION

    Inventor： Georgios Dogiamis ,  Sasha Oster ,  Johanna Swan ,  Shawna Liff ,  Adel Elsherbini ,  Telesphor Kamgaing ,  Aleksandar Aleksov

    IPC: H01L23/66 ,  H01P3/12

    CPC classification number: H01L23/66 ,  H01P3/121 ,  H01L2223/6627

    Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.

    Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
    90.
    发明授权
    Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices 有权

    公开(公告)号：US11823972B2

    公开(公告)日：2023-11-21

    申请号：US16040746

    申请日：2018-07-20

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

    IPC: H01L23/367 ,  H01L25/065 ,  H01L23/498 ,  H01L23/373

    CPC classification number: H01L23/367 ,  H01L23/3737 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06517

    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

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